Package Marking
All Virtex-6 devices have package top-markings similar to the example shown in Figure6-1 and explained in Table6-1.
Note:The informational product change customer notice XCN11022: Product Marking Change outlines a change to the top marking process from an ink mark to laser marking. The previous top mark included an ink patch.
X-Ref Target - Figure 6-1Device TypePackageXC6VLX130TFFG1156xxxXXXXDDxxxxxxxA1C ESDate CodeLot CodeEngineering SampleSpeed GradeOperating Rangeug365_c6_01_081518Figure 6-1:
Table 6-1:
ItemXilinx LogoFamily Brand LogoPb-Free Logo1st Line
Virtex-6 Device Package Marking
Xilinx Device Marking Definition—Example
Definition
Xilinx logo, Xilinx name with trademark, and trademark-registered status.
Virtex-6 family name with trademark and trademark-registered status. This line is optional and could appear blank.
If the Pb-Free logo appears, the package is RoHS compliant. If the logo does not appear, the package is RoHS compliant if it has the G detailed in the 2nd Line definition below.Device type.
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
Chapter 5:Thermal Specifications
Table5-1 shows the thermal resistance data for Virtex-6 devices (grouped in the packages offered). The data includes junction-to-ambient in still air, junction-to-case, and junction-to-board data based on standard JEDEC four-layer measurements.
Note:The data in Table5-1 is for device/package comparison purposes only. Do not apply directly to your system design. Attempts to recreate this data are only valid using the steady-state measurement technique outlined in JESD51-2a, JESD51-6, and JESD51-8.
Table 5-1:Package
FF484FFG484
Thermal Resistance Data—All DevicesPackageBody Size
23x23
Devices
XC6VLX75TXC6VLX130TXC6VLX75T
θJA(°C/W)
13.112.611.811.210.910.89.79.59.59.510.09.99.89.69.69.3
θJB(°C/W)
3.53.13.53.12.92.72.52.32.32.32.92.72.62.42.42.1
θJC(°C/W)
0.280.170.280.170.140.110.090.060.060.060.160.120.100.080.080.10
θJA (°C/W)@ 250 LFM
8.98.37.57.17.06.85.85.65.65.66.16.05.95.75.75.4
θJA (°C/W)@ 500 LFM
7.47.06.46.05.85.74.84.64.64.65.15.04.94.74.74.4
θJA (°C/W)@ 750 LFM
6.86.45.85.45.35.24.34.14.14.14.64.54.44.24.24.0
FF784FFG784RF784
29x29
XC6VLX130TXQ6VLX130TXC6VLX195TXC6VLX240TXQ6VLX240T
FF1154FFG1154FF1155FFG1155
35x35
XC6VHX250TXC6VHX380TXC6VHX255TXC6VHX380TXC6VLX130TXQ6VLX130TXC6VLX195T
35x35
FF1156FFG1156RF1156
35x35
XC6VLX240TXQ6VLX240TXC6VLX365TXC6VSX315TXQ6VSX315TXC6VSX475TXQ6VSX475T
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
Chapter 5:Thermal Specifications
determined by those using these guidelines. For complete information on package moisture / reflow classification and package reflow conditions, refer to the Joint IPC/JEDEC Standard J-STD-020C.
Sn/Pb Reflow Soldering
Figure5-4 shows typical conditions for solder reflow processing of Sn/Pb soldering using IR/convection. Both IR and convection furnaces are used for BGA assembly. The moisture sensitivity of PSMCs must be verified prior to surface-mount flow.
X-Ref Target - Figure 5-4TMAX (body) = 220°CTMAX (leads) = 235°C 2–4°C/sTemperature (°C)Ramp down2–4°C/sT = 183°Ct183Preheat & drying dwell120–180 s between95–180°C (Note 3)(Note 2)60s < t183< 120sapplies to lead areaTime (s)ug365_c5_04 _061714Figure 5-4:Typical Conditions for IR Reflow Soldering of Sn/Pb Solder
Notes for Figure5-4:
1.2.3.4.
Maximum temperature range = 220°C (body). Minimum temperature range before205°C (leads/balls).
Preheat drying transition rate 2–4°C/sPreheat dwell 95–180°C for 120–180 secondsIR reflow must be performed on dry packages
Pb-Free Reflow Soldering
Xilinx uses SnAgCu (SAC305) solder balls for BGA packages. In addition, suitable material are qualified for the higher reflow temperatures (245°C–250°C) required by Pb-free
soldering processes. Xilinx recommends soldering SAC305 BGA packages with SAC305 solder paste.
The optimal profile must take into account the solder paste/flux used, the size of the
board, the density of the components on the board, and the mix between large components and smaller, lighter components. Profiles should be established for all new board designs using thermocouples at multiple locations on the component. In addition, if there is a mixture of devices on the board, then the profile should be checked at various locations on the board. Ensure that the minimum reflow temperature is reached to reflow the larger components and at the same time, the temperature does not exceed the threshold temperature that might damage the smaller, heat sensitive components.Table5-4 and Figure5-5 provide guidelines for profiling Pb-free solder reflow.
In general, a gradual, linear ramp into a spike has been shown by various sources to be the optimal reflow profile for Pb-free solders (Figure5-5). SAC305 alloy reaches full liquidus
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
Soldering Guidelines
temperature at 235°C. When profiling, identify the possible locations of the coldest solder joints and ensure that those solder joints reach a minimum peak temperature of 235°C for at least 10 seconds. It might not be necessary to ramp to peak temperatures of 260°C. Reflowing at high peak temperatures of 260°C and above can damage the heat sensitive components and cause the board to warp.
Users should reference the latest IPC/JEDEC J-STD-020 standard for the allowable peak temperature on the component body. The allowable peak temperature on the component body is dependent on the size of the component. Refer to Table5-4 for peak package reflow body temperature information. In any case, use a reflow profile with the lowest peak temperature possible.
Table 5-4:Pb-Free Reflow Soldering Guidelines
Profile Feature
Ramp-up rate
Preheat Temperature 150°–200°CTemperature maintained above 217°C
Convection, IR/Convection
2°C/s maximum60–120 seconds
60–150 seconds (60–90 seconds typical)
Time within 5°C of actual peak temperature30 seconds maximumPeak Temperature (lead/ball)Peak Temperature (body)Ramp-down Rate
Time 25°C to Peak Temperature
235°C minimum, 245°C typical (depends on solder paste, board size, components mixture)245°C–250°C, package body size dependent (reference Table5-5)2°C/s maximum
3.5 minutes minimum, 5.0 minutes typical, 8minutes maximum
X-Ref Target - Figure 5-5Tbody (MAX) = 245–250°C (package type dependent)See data sheet for maximum value by package typeTlead (MIN) = 235–250°C (10s minimum)Ramp down 2°C/s maxTemperature (°C)217°C t217Wetting time = 60–150 s150–200°CRamp up 2°C/s maxPreheating60–120sTime (s)ug365_c5_05_110414Figure 5-5:Typical Conditions for Pb-Free Reflow Soldering
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
Chapter 6:Package Marking
Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2024
FPGA可编程逻辑器件芯片XCZU15EG-1FFVB1156E中文规格书 - 图文
