Generating PROM Files
in x16 mode. The FPGA now knows on which bus width to receive the rest of the data. No packet processed by the FPGA until the Sync word is found. See Table5-7.Table 5-7:Sync Word
31:240xAA
23:160x99
15:80x55
7:00x66
Generating PROM Files
PROM files are generated from bitstream files with the PROMGen utility. Users can access PROMGen directly from the command line or indirectly through the iMPACT File
Generation Mode. For PROMGen syntax, refer to UG628, Command Line Tools User Guide. For information on iMPACT software, refer to the ISE? software documentation. PROM files serve to reformat bitstream files for PROM programming and combine bitstream files for serial daisy-chains (see PROM Files for Serial Daisy-Chains).
PROM Files for Serial Daisy-Chains
Configuration data for serial daisy-chains requires special formatting because separate BIT files cannot simply be concatenated together to program the daisy-chain. The special formatting is performed by PROMGen (or iMPACT software) when generating a PROM file from multiple bitstreams. To generate the PROM file, specify multiple bitstreams using the PROMGen -n, -u, and -d options or the iMPACT Software File Generation Wizard. Refer to ISE software documentation for details.
PROMGen reformats the configuration bitstreams by nesting downstream configuration data into configuration packets for upstream devices. Attempting to program the chain by sending multiple bitstreams to the first device causes the first device to configure and then ignore the subsequent data.
PROM Files for SelectMAP Configuration
The MCS file format is most commonly used to program Xilinx? configuration PROMs that in turn program a single FPGA in SelectMAP mode. For custom configuration
solutions, the BIN and HEX files are the easiest PROM file formats to use due to their raw data format. In some cases, additional formatting is required; refer to XAPP502, Using a Microprocessor to Configure Xilinx FPGAs via Slave Serial or SelectMAP Mode for details.If multiple configuration bitstreams for a SelectMAP configuration reside on a single
memory device, the bitstreams must not be combined into a serial daisy-chain PROM file. Instead, the target memory device should be programmed with multiple BIN or HEX files. If a single PROM file with multiple, separate data streams is needed, one can be generated in iMPACT software by targeting a Parallel PROM, then selecting the appropriate number of data streams. This can also be accomplished through the PROMGen command line. Refer to PROMGen software documentation for details.
PROM Files for SPI/BPI Configuration
The -d, -u, -spi, -s, and -data_width options in PROMGen or the iMPACT Software File Generation Wizard are used to create PROM files for third-party flash devices. The output format supported by the third-party programmer is important. Some BPI devices require endian-swapping to be enabled when programming the PROM file. Refer to the flash vendor's documentation.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 5:Configuration Details
Advanced Encryption Standard Overview
Creating an Encrypted Bitstream
BitGen, provided with the ISE software, can generate encrypted as well as non-encrypted bitstreams. For AES bitstream encryption, the user specifies a 256-bit key as an input to BitGen. BitGen in turn generates an encrypted bitstream file (BIT) and an encryption key file (NKY).
For specific BitGen commands and syntax, refer to UG628, Command Line Tools User Guide.
Loading the Encryption Key
The encryption key can only be loaded onto a Spartan-6 device through the JTAG interface. The iMPACT tool, provided with ISE software, can accept the NKY file as an input and program the device with the key through JTAG, using a Xilinx USB-II programming cable.To program the key, the device enters a special key-access mode using the
ISC_PROGRAM_KEY instruction. In this instruction, all FPGA memory, including the encryption key and configuration memory, is cleared. After the key is programmed and the key-access mode is exited and the Key Security bits are programmed, the key cannot be read out of the device by any means, and it cannot be reprogrammed without clearing the entire device. After programming the key into the eFUSE, the key cannot be reprogrammed later.
Loading Encrypted Bitstreams
Once the device has been programmed with the correct encryption key, the device can be configured with an encrypted bitstream. After configuration with an encrypted bitstream, it is not possible to read the configuration memory through JTAG or SelectMAP readback, regardless of the BitGen security setting.
While the device holds an encryption key, a non-encrypted bitstream can be used to configure the device; in this case the key is ignored. After configuring with a non-encrypted bitstream, readback is possible (if allowed by the BitGen security setting). The encryption key still cannot be read out of the device, preventing the use of Trojan Horse bitstreams to defeat the Spartan-6 FPGA encryption scheme.
The method of configuration is not affected by encryption. The configuration bitstream can be delivered in any x1 or x8 data width configuration mode (Serial, SPI x1, JTAG, BPI, SelectMAP). The SPI x2, SPI x4, BPI x16, and SelectMAP x16 bus widths are not supported for encrypted bitstreams. Configuration timing and signaling are also unaffected by encryption.
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Chapter 5:Configuration Details
Control Register 0 (CTL)
The CTL register is used to configure the Spartan-6 device. Writes to the CTL register are masked by the value in the MASK register. The name of each bit position in the CTL0 register is given in Table5-34.
Table 5-34:
Control Register 0 (CTL0) Description
Bit Index
6
Description
Decryption
0: No decryption
1: Decryption used (automatically set SBITS to Level1 or up and mc_enc=1)
Once set to 1, the DEC cannot be altered except by hard reboot (PROGRAM_B or JPROGRAM).
Security level:
Level0: SBITS=00: R/W OK (default)
Level1: SBITS=01: Permits only ICAP readbackLevel2: SBITS=10: All readback disabled; (en_vrb_b =1 => Vrd=0)
Level3: SBITS=11: Readback disabled, Writing disabled except CRC,CMD; (mc_vrd=1 => Vrd=0)
Once set to 1, the SBITS cannot be altered except by soft reboot (PROGRAM_B, JPROGRAM, IPROG command, error reboot, or fallback reboot).
PERSIST
3
Configuration interface remains after configuration0: No (default)1: Yes
USE_EFUSE_KEY
2
Use eFUSE key as decryption key
0: Use battery-backed RAM key (default)1: Use eFUSE key
External CRC status pin (INIT_B) pulled Low when using POST CRC.
The first configuration always has the CRC indicator on INIT_B.
0: CRC indicator enabled1: CRC indicator disabled
RESERVED
0
Reserved.
100
BitGen Default
0
Name
DEC
SBITS5:400
CRC_EXTSTAT_DISABLE10
Caution!PERSIST and ICAP cannot be set at the same time. PERSIST has higher priority.
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
FPGA可编程逻辑器件芯片XC2V80-4FF1152I中文规格书
