Chapter 2: XPHY Architecture
?Voltage and Temperature Compensation: Compensates for voltage and temperature changes.Voltage and temperature compensation (VTC) uses round-robin scheduling to automaticallyupdate delays lines based on voltage and temperature drift without interrupting normaloperation of the associated XPHY NIBBLESLICE.
TIP: When using inter-byte or inter-nibble clocking, each nibble can require a different amount of time tocomplete the same BISC step. In this case, the next BISC step cannot be started until all nibbles finish thecurrent step.
Controlling Built-in Self-Calibration
The only attribute required to run BISC is SELF_CALIBRATE = ENABLE. The following tableshows BISC-related attributes and how they are overridden if BISC is not used
(SELF_CALIBRATE = DISABLE). For more complete attribute descriptions, see Attributes.Table 13: BISC-Related Attributes
Attribute
CRSE_DLY_ENDELAY_VALUE_<0-5>
Description
Enables CRSE delays
Sets the initial input and output delayline value in each NIBBLESLICE.Disables VTC on input delaysDisables VTC on output delaysDisables VTC on QTR delays
Controls strobe (p-clk and n-clk in thiscase) centering for source-synchronous interfaces
Effect From SELF_CALIBRATE = DISABLE
Coarse delays are not used.
DELAY_VALUE_<0-5> loads a zero delay to input andoutput delays. However, delays can still be loadedfrom the PL.
Disables VTC on input delaysDisables VTC on output delaysDisables VTC on QTR delays
RX_CLK_PHASE_N and RX_CLK_PHASE_P cannot beset to SHIFT_90
DIS_IDLY_VT_TRACKDIS_ODLY_VT_TRACKDIS_QDLY_VT_TRACKRX_CLK_PHASE_N,RX_CLK_PHASE_P
The following table shows how to control BISC.
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Chapter 2: XPHY Architecture
Table 14: Controlling BISC Steps Summary
BISC Step
Alignment
Controlled byOther ConsiderationsCommon to All
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Assert RX_EN_VTC and
TX_EN_VTC during the resetsequence to perform
alignment. Refer to ResetSequence.
Assert RX_EN_VTC and
TX_EN_VTC during the resetsequence to perform delaycalibration. Refer to ResetSequence.
When DLY_RDY asserts, bothBISC alignment and delaycalibration are complete.From this point forwarddelays can be changed. Ifmultiple nibbles comprise aninterface, the assertion timefor DLY_RDY can vary foreach nibble. Within
simulation, the assertiontime of DLY_RDY does notvary for each nibble in aninterface, but varies as theXPHY configuration andconnections change.DLY_RDY can take up to 1.3ms to assert
After PHY_RDY asserts, theinterface is ready to undergoVTC
When EN_VTC = 1, QTR
delays and the delay withinthe tristate NIBBLESLICEundergo VTC. This is notdependent upon RX/TX_EN_VTC. VTC on thetristate signal is not
supported on NIBBLESLICEsaffected by TBYTE_CTRL_# =T, only for TBYTE_CTRL_# =PHY_WREN.
When EN_VTC = 1 and therelevant RX/TX_EN_VTC = 1,input and output delays alsoundergo VTC
For output delays, VTCcompensates for the valueset in DELAY_VALUE_#. Forinput delays, the taps thatVTC operates on is not asstraightforward due to
align_delay. See ControllingDelays for more informationon how align_delay andDELAY_VALUE_# interactwith VTC for input delays.If external calibration is notrequired and VTC is beingused, tie off EN_VTC = 1
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Alignment is only performedonce upon completion of thereset sequence. To re-perform alignment, resetthe XPHY.
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SELF_CALIBRATE must be setto TRUE for any BISC stepsto occur
BISC is consideredcompleted when:
○
Delay Calibration
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If the interface is usingall steps of BISC, whenPHY_RDY assertsIf the interface is usingBISC without VTC, whenDLY_RDY assertsIf the interface is notusing BISC, thenDLY_RDY asserting
indicates that delays canbe changed, but not thatalignment and delay
calibration are complete.Because BISC is not usedin this scenario, it neverstarts or completes.
○
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○
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VTC
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Applied to input, output, andquarter delays
Can be disabled through theDIS_IDLY_VT_TRACK (inputdelays), DIS_ODLY_VT_TRACK(output delays), and
DIS_QDLY_VT_TRACK (QTRdelays) attributesCoarse delays cannotundergo VTC
When simulating, some ofthe BISC control ports(BISC_START_IN,BISC_STOP_IN,
BISC_START_OUT, andBISC_STOP_OUT) must bedaisy chained with othernibbles for BISC to be
supported. The daisy chainis agnostic to the order inwhich nibbles are
connected, and unusednibbles do not need to bepart of the daisy chain. Formore information, see Ports.
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Chapter 2: XPHY Architecture
IMPORTANT! The DELAY_VALUE_x attribute and VTC are not supported if REFCLK_FREQUENCY is lessthan 500 MHz. In this scenario, EN_VTC should be tied to 0.
The steps before/after changing delays differ if PHY_RDY was asserted for the first time, as
described in the following sequences. If not using VTC, refer to the Controlling Delays section forhow to change delay values.
The following sequence and figure show the before/after steps of changing delay values onNIBBLESLICE[x] after PHY_RDY is asserted for the first time:1.Start with EN_VTC, RX_EN_VTC, and TX_EN_VTC asserted.2.Deassert RX_EN_VTC and TX_EN_VTC.
3.After RX_EN_VTC and TX_EN_VTC have been deasserted, wait ten CTRL_CLK cycles.4.Modify delay values (see Controlling Delays).
5.Wait another ten CTRL_CLK cycles, then reassert RX_EN_VTC and TX_EN_VTC.6.The XPHY is ready to undergo VTC and can be operated normally.
Figure 18: Changing Delay Values After PHY_RDY is Asserted for the First Time
The following sequence and figure show the before/after steps of changing delay values onNIBBLESLICE[x] before PHY_RDY is asserted for the first time:
1.Start with EN_VTC deasserted, and RX_EN_VTC and TX_EN_VTC asserted.2.After DLY_RDY asserts, deassert RX_EN_VTC and TX_EN_VTC.
3.After the relevant RX_EN_VTC and TX_EN_VTC is deasserted, wait ten CTRL_CLK cycles.4.Modify delay values (see Controlling Delays).
5.Wait another ten CTRL_CLK cycles, then assert EN_VTC, RX_EN_VTC, and TX_EN_VTC.6.After PHY_RDY asserts, the XPHY is ready to undergo VTC and can be operated normally.
Figure 19: Changing Delay Values Before PHY_RDY is Asserted for the First Time
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FPGA可编程逻辑器件芯片XC2V1000-5BG728I中文规格书
