AD7708/AD7718
The output code for any analog input voltage on the AD7708can be represented as follows:Code = (AIN × GAIN × 216)/(1.024 × VREF)whereAIN is the analog input voltage,GAIN is the PGA gain, i.e., 1 on the 2.5 V range and 128 onthe 20 mV range.When an ADC is configured for bipolar operation, the coding isoffset binary with a negative full-scale voltage resulting in a codeof 000 . . . 000, a zero differential voltage resulting in a code of100 . . . 000, and a positive full-scale voltage resulting in a codeof 111 . . . 111. The output code from the AD7718 for anyanalog input voltage can be represented as follows:Code = 223 × [(AIN × GAIN/(1.024 × VREF)) + 1]whereAIN is the analog input voltage,GAIN is the PGA gain, i.e., 1 on the ±2.5 V range and 128 onthe ±20 mV range.The output code from the AD7708 for any analog input voltagecan be represented as follows:Code = 215 × [(AIN × GAIN/(1.024 × VREF)) + 1]whereAIN is the analog input voltage,GAIN is the PGA gain, i.e., 1 on the ±2.5 V range and 128 onthe ±20 mV range.Oscillator Circuitthe ADC is configured in five fully-differential or 10 pseudo-differential input channel mode, the REFSEL bit setting isirrelevant as only one reference input is available.The common-mode range for these differential inputs is fromAGND to AVDD. The reference inputs are unbuffered andtherefore excessive R-C source impedances will introduce gainerrors. The nominal reference voltage for specified operation,VREF, (REFIN1(+)–REFIN1(–) or REFIN2(+)–REFIN2(–)),is 2.5 V, but the AD7708/AD7718 is functional with referencevoltages from 1 V to AVDD. In applications where the excitation(voltage or current) for the transducer on the analog input alsodrives the reference voltage for the part, the effect of the lowfrequency noise in the excitation source will be removed as theapplication is ratiometric. If the AD7708/AD7718 is used in anonratiometric application, a low noise reference should beused. Recommended reference voltage sources for the AD7708/AD7718 include the AD780, REF43, and REF192. It shouldalso be noted that the reference inputs provide a high impedance,dynamic load. Because the input impedance of each referenceinput is dynamic, resistor/capacitor combinations on these inputscan cause dc gain errors, depending on the output impedance ofthe source that is driving the reference inputs. Reference voltagesources, like those recommended above (e.g., AD780) will typicallyhave low output impedances and are therefore tolerant of havingdecoupling capacitors on the REFIN(+) without introducing gainerrors in the system. Deriving the reference input voltage acrossan external resistor will mean that the reference input sees asignificant external source impedance. External decoupling onthe REFIN(+) and REFIN(–) pins would not be recommendedin this type configuration.RESET InputThe AD7708/AD7718 is intended for use with a 32.768 kHzwatch crystal or ceramic resonator. A PLL internally locks ontoa multiple of this frequency to provide a stable 4.194304 MHzclock for the ADC. The modulator sample rate is the same asthe oscillator frequency.The start-up time associated with 32 kHz crystals is typically300 ms. The OSPD bit in the mode register can be used toprevent the oscillator from powering down when the AD7708/AD7718 is placed in power-down mode. This avoids having towait 300 ms after exiting power-down to start a conversion atthe expense of raising the power-down current.Reference InputThe RESET input on the AD7708/AD7718 resets all the logic,the digital filter and the analog modulator while all on-chipregisters are reset to their default state. RDY is driven high andthe AD7708/AD7718 ignores all communications to any of itsregisters while the RESET input is low. When the RESET inputreturns high the AD7708/AD7718 operates with its default setupconditions and it is necessary to set up all registers and carry outa system calibration if required after a RESET command.Power-Down ModeThe AD7708/AD7718 has a fully differential reference inputcapability. When the AD7708/AD7718 is configured in 8-channelmode (CHCON = 0) the user has the option of selecting one oftwo reference options. This allows the user to configure somechannels, for example, for ratiometric operation while others canbe configured for absolute value measurements. The REFSEL bitin the mode register allows selection of the required reference.If the REFSEL bit is cleared, the reference selected is REFIN1(+)–REFIN1(–) for the active channel. If this bit is set, the refer-ence selected is REFIN2(+) – REFIN2(–) for the active channel.When the AD7708/AD7718 is configured in 10-channel mode(CHCON = 1) the user has only one reference option (REFIN1).The contents of the CHCON bit overrides the REFSEL bit. IfLoading 0, 0, 0 to the MD2, MD1, MD0 bits in the ADC moderegister places the ADC in device power-down mode. Devicepower-down mode is the default condition for the AD7708/AD7718 on power-up. The ADC retains the contents of all itson-chip registers (including the data register) while in power-down. The device power-down mode does not affect the digitalinterface, but does affect the status of the RDY pin. Writing theAD7708/AD7718 into power-down will reset the RDY line high.Placing the part in power-down mode reduces the total current(AIDD + DIDD) to 31μA max when the part is operated at 5 Vand the oscillator allowed to run during power-down mode.With the oscillator shut down the total IDD is typically 9 μA.REV. 0–39–
AD7708/AD7718
CalibrationThe AD7708/AD7718 provides four calibration modes that canbe programmed via the mode bits in the mode register. One ofthe major benefits of the AD7708/AD7718 is that it is factory-calibrated with chopping enabled as part of the final test processwith the generated coefficients stored within the ADC. At power-on, the factory gain calibration coefficients are automaticallyloaded to the gain calibration registers on the AD7708/AD7718.This gives excellent offset and drift performance and it isenvisaged that in the majority of applications the user will notneed to perform any field calibrations. Also, because factorygain calibration coefficients (generated at 25°C ambient) areautomatically present at power-on, an internal full-scale calibrationwill only be required if the part is being operated at temperaturessignificantly different from 25°C.When chopping is disabled (CHOP =1) the AD7708/AD7718requires an offset calibration or new calibration coefficients onrange changing or when significant temperature changes occuras the signal chain is no longer chopped and offset and drifterrors are no longer removed as part of the conversion process.The factory-calibration values for any one channel will be over-written if any one of the four calibration options is initiated.The AD7708/AD7718 offers “internal” or “system” calibrationfacilities. For full calibration to occur, the calibration logic mustrecord the modulator output for two different input conditions.These are “zero-scale” and “full-scale” points. These pointsare derived by performing a conversion on the different inputvoltages provided to the input of the modulator during calibration.The result of the “zero-scale” calibration conversion is stored inthe Offset Calibration Registers for the appropriate channel.The result of the “full-scale” calibration conversion is storedin the Gain Calibration Registers. With these readings, thecalibration logic can calculate the offset and the gain slope forthe input-to-output transfer function of the converter. During an“internal” zero-scale or full-scale calibration, the respective“zero” input and “full-scale” input are automatically connectedto the ADC input pins internally to the device. A “system” cali-bration, however, expects the system zero-scale and systemfull-scale voltages to be applied to the external ADC pinsbefore the calibration mode is initiated. In this way externalADC errors are taken into account and minimized as a resultof system calibration. It should also be noted that to optimizecalibration accuracy, all AD7708/AD7718 ADC calibrationsare carried out automatically at the slowest update rate withchop enabled. When chop mode is disabled calibrations arecarried out at the update rate defined by the SF word in thefilter register.Internally in the AD7708/AD7718, the coefficients are normalizedbefore being used to scale the words coming out of the digitalfilter. The offset calibration coefficient is subtracted from theresult prior to the multiplication by the gain coefficient. Withchopping disabled AD7708/AD7718 ADC specifications willonly apply after a zero-scale calibration at the operating point ofinterest. From an operational point of view, a calibration shouldbe treated like another ADC conversion. A zero-scale calibration(if required) should always be carried out before a full-scalecalibration. System software should monitor the RDY bit in theSTATUS register to determine end of calibration via a pollingsequence or interrupt driven routine.Grounding and LayoutSince the analog inputs and reference inputs are differential,most of the voltages in the analog modulator are common-modevoltages. The excellent common-mode rejection of the part willremove common-mode noise on these inputs. The analog anddigital supplies to the AD7708/AD7718 are independent andseparately pinned out to minimize coupling between the analogand digital sections of the device. The AD7708/AD7718 can beoperated with 5 V analog and 3 V digital supplies or vice versa.The digital filter will provide rejection of broadband noise onthe power supplies, except at integer multiples of the modulatorsampling frequency. The digital filter also removes noise fromthe analog and reference inputs provided these noise sources donot saturate the analog modulator. As a result, the AD7708/AD7718 is more immune to noise interference than a conventionalhigh-resolution converter. However, because the resolution of theAD7708/AD7718 is so high and the noise levels from theconverter so low, care must be taken with regard to groundingand layout.The printed circuit board that houses the ADC should be designedso the analog and digital sections are separated and confined tocertain areas of the board. This facilitates the use of ground planesthat can be easily separated. A minimum etch technique isgenerally best for ground planes as it gives the best shielding.Although the AD7708/AD7718 has separate pins for analog anddigital ground, the AGND and DGND pins are tied togetherinternally via the substrate. Therefore, the user must not tiethese two pins to separate ground planes unless the groundplanes are connected together near the AD7708/AD7718.In systems where the AGND and DGND are connected some-where else in the system, i.e., the systems power supply, theyshould not be connected again at the AD7708/AD7718 or aground loop will result. In these situations it is recommended thatground pins of the AD7708/AD7718 be tied to the AGND plane.In any layout it is implicit that the user keep in mind the flow ofcurrents in the system, ensuring that the paths for all currentsare as close as possible to the paths the currents took to reachtheir destinations. Avoid forcing digital currents to flow throughthe AGND.Avoid running digital lines under the device as these will couplenoise onto the die. The analog ground plane should be allowedto run under the AD7708/AD7718 to prevent noise coupling.The power supply lines to the AD7708/AD7718 should use aswide a trace as possible to provide low impedance paths andreduce the effects of glitches on the power supply line. Fastswitching signals like clocks should be shielded with digitalground to avoid radiating noise to other sections of the boardand clock signals should never be run near the analog inputs.Avoid crossover of digital and analog signals. Traces on oppositesides of the board should run at right angles to each other. This willreduce the effects of feedthrough through the board. A microstriptechnique is by far the best, but is not always possible with adouble-sided board. In this technique, the component side ofthe board is dedicated to ground planes while signals are placedon the solder side.–40–REV. 0
半导体传感器AD7714YRUZ中文规格书 - 图文
