Chapter 7:Readback and Configuration Verification
X-Ref Target - Figure 7-2CSI_BRDWR_B
WRITEREADWRITED[0:7]CCLK
AA9955662800E000XXXXXXXXXX30UG191_c7_02_110811Figure 7-2:SelectMAP Status Register Read
To read registers other than STAT, the address specified in the Type-1 packet header in step2 of Table7-1 should be modified and the word count changed if necessary. Reading from the FDRO register is a special case that is described in “Configuration Memory Read Procedure (SelectMAP).”
Configuration Memory Read Procedure (SelectMAP)
The process for reading configuration memory from the FDRO register is similar to the process for reading from other registers. Additional steps are needed to accommodate the configuration logic. Configuration data coming from the FDRO register passes through the frame buffer. The first frame of readback data should be discarded.1.2.3.4.5.6.7.8.
Write the Bus Width detection sequence and Synchronization word to the device.Write one NOOP command.
Write the Shutdown command, and write one NOOP command.
Write the RCRC command to the CMD register, and write one NOOP command.Write five NOOP instructions to ensure the shutdown sequence has completed. DONE goes Low during the shutdown sequence.
Write the RCFG command to the CMD register, and write one NOOP command.Write the Starting Frame Address to the FAR (typically 0x00000000).
Write the read FDRO register packet header to the device. The command read count tobe sent to the ICAP will have an additional (one) word, specific to the 8-bit SelectMapinterface, given by:
FDRO Command Word Count = (words to be read) + 1The data returned will be:
FDRO Read Length = (words per frame) x (frames to read + 1)
One extra frame is read to account for the frame buffer. Users should strobe readbackdata while DOUT_BUSY is Low. The frame buffer produces one dummy frame at thebeginning of the read. Also, one extra word is read in SelectMap8 mode.9.
Write 32 NOOP commands to the device to flush the packet buffer.
10.Read the FDRO register from the SelectMAP interface. The FDRO read length is the
same as in step 9 above.11.Write one NOOP instruction.
12.Write the START command, and write one NOOP command.
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Readback Command Sequences
13.Write the RCRC command, and write one NOOP command.14.Write the DESYNCH command.
15.Write at least 64 bits of NOOP commands to flush the packet buffer. Continue sending
CCLK pulses until DONE goes High.Table7-2 shows the readback command sequence.
Table 7-2:Step
Shutdown Readback Command Sequence (SelectMAP)SelectMAP PortDirection
Configuration Data
FFFFFFFF000000BB
Dummy WordBus Width Sync WordBus Width DetectDummy WordSync Word
Type 1 NOOP Word 0Type 1 Write 1 Word to CMDSHUTDOWN CommandType 1 NOOP Word 0Type 1 Write 1 Word to CMDRCRC CommandType 1 NOOP Word 0Type 1 NOOP Word 0Type 1 NOOP Word 0Type 1 NOOP Word 0Type 1 NOOP Word 0Type 1 NOOP Word 0Type 1 Write 1 Word to CMDRCFG CommandType 1 NOOP Word 0Type 1 Write 1 Word to FARFAR Address = 00000000Type 1 Read 0 Words from FDROType 2 Read 147,600 Words from FDROType 1 NOOP Word 0
Type 1 31 more NOOPs Word 0Packet Data Read FDRO Word 0
Explanation
1Write
11220044FFFFFFFFAA995566
23
WriteWrite
20000000300080010000000B2000000030008001
4Write
00000007200000002000000020000000
5Write
20000000200000002000000030008001
6Write
0000000420000000
789
WriteWriteWrite
3000200100000000280060004802409020000000...00000000
1011
ReadWrite
...0000000020000000
Packet Data Read FDRO Word 147599Type 1 NOOP Word 0
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Chapter 7:Readback and Configuration Verification
Configuration Memory Read Procedure (1532 JTAG)
The IEEE 1532 JTAG readback procedure differs slightly from the IEEE 1149.1 JTAG readback procedure in that readback commands are not sent to the configuration logic through the CFG_IN JTAG register, rather the ISC_READ JTAG register is used to read configuration memory directly.
At the end of 1532 JTAG readback, the CRC Error status must be cleared by issuing a Reset CRC command or writing the correct CRC value to the CRC register. The 1532 JTAG readback procedure is illustrated in Figure7-3.
STARTALoad ISC_ENABLELoad ISC_READLoad 5'b00000RTI minimum12 TCK cyclesLoad ISC_PROGRAMRTI1 TCK cycleShift 37 bits ofreadback data +statusNEODataYLoad ISC_PROGRAMLoad Reset CRCcommandLoad ISC_DISABLERTI minimum12 TCK cyclesGo to Test Logic ResetLoad 32 bits ofbitstream dataRTI1 TCK cycleNEObitstreamYASTOPUG191_c7_03_050406
Figure 7-3:IEEE 1532 JTAG Readback Flow
Table7-7 lists the readback files.Table 7-7:Readback FilesFileExtension
File Type
BitGen Setting -b and -g
Readback
Description
An ASCII file that contains readback commands, rather than configuration commands, and expected readback data where the configuration data normally is. This file must be used with the MSK file
Binary version of the RBA file. This file must be used with the MSK file.
An ASCII file that contains only expected readback data, including the initial pad frame. No commands are included. This file must be used with the MSD file.
RBAASCII
RBBBinary
-g
Readback
RBDASCII
-g
Readback
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Verifying Readback Data
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Chapter 7:Readback and Configuration Verification
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
FPGA可编程逻辑器件芯片XC2S150E-7FG676I中文规格书 - 图文
