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FPGA可编程逻辑器件芯片EP2AGX95EF29C5N中文规格书 - 图文

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AIIGX51002-2.0

This chapter describes the features of the logic array block (LAB) in the Arria?II core fabric. The LAB is composed of basic building blocks known as adaptive logic modules (ALMs) that you can configure to implement logic functions, arithmetic functions, and register functions.

This chapter contains the following sections:

■■

“Logic Array Blocks” on page2–1“Adaptive Logic Modules” on page2–5

Logic Array Blocks

Each LAB consists of ten ALMs, various carry chains, shared arithmetic chains, LAB control signals, local interconnect, and register chain connection lines. The local interconnect transfers signals between ALMs in the same LAB. The direct link interconnect allows the LAB to drive into the local interconnect of its left and right neighbors. Register chain connections transfer the output of the ALM register to the adjacent ALM register in the LAB. The Quartus? II Compiler places associated logic in the LAB or the adjacent LABs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency.

Figure2–1 shows the ArriaII LAB structure and the LAB interconnects.

Figure2–1.LAB Structure in ArriaII Devices

C4C12Row Interconnects ofVariable Speed & LengthR20R4ALMsDirect link

interconnect from adjacent block

Direct linkinterconnect fromadjacent block

Direct link

interconnect toadjacent block

Direct linkinterconnect toadjacent block

Local InterconnectLABMLABColumn Interconnects ofLocal Interconnect is Driven Variable Speed & Lengthfrom Either Side by Column Interconnect & LABs, & from Above by Row Interconnect

Arria II Device Handbook Volume 1: Device Interfaces and IntegrationDecember 2010

Chapter 2:Logic Array Blocks and Adaptive Logic Modules in ArriaII Devices

Logic Array Blocks

The LAB of the Arria II device has a derivative called memory LAB (MLAB), which adds look-up table (LUT)-based SRAM capability to the LAB. The MLAB supports a maximum of 640bits of simple dual-port SRAM. You can configure each ALM in an MLAB as either a 64 × 1 or 32 × 2 block, resulting in a configuration of 64 × 10 or

32 × 20 simple dual-port SRAM blocks. MLAB and LAB blocks always coexist as pairs in ArriaII devices. MLAB is a superset of the LAB and includes all LAB features. Figure2–2 shows an overview of LAB and MLAB topology.

fFor more information about MLABs, refer to the TriMatrix Memory Blocks in ArriaII

Devices chapter.

Figure2–2.LAB and MLAB Structure in ArriaII Devices

(1)LUT-based-64 x 1Simple dual port SRAM(1)LUT-based-64 x 1Simple dual port SRAMALMALMLUT-based-64 x 1(1)Simple dual port SRAMLUT-based-64 x 1(1)Simple dual port SRAMLUT-based-64 x 1(1)Simple dual port SRAMALMALMALMLAB Control BlockLUT-based-64 x 1(1)Simple dual port SRAMLUT-based-64 x 1(1)Simple dual port SRAMLUT-based-64 x 1(1)Simple dual port SRAMLUT-based-64 x 1(1)Simple dual port SRAMLUT-based-64 x 1(1)Simple dual port SRAMLAB Control BlockALMALMALMALMALMMLABNote to Figure2–2:

LAB(1)You can use an MLAB ALM as a regular LAB ALM or configure it as a dual-port SRAM.

Arria II Device Handbook Volume 1: Device Interfaces and Integration

Chapter 2:Logic Array Blocks and Adaptive Logic Modules in ArriaII DevicesLogic Array Blocks

Arria II Device Handbook Volume 1: Device Interfaces and Integration

Chapter 2:Logic Array Blocks and Adaptive Logic Modules in ArriaII Devices

Logic Array Blocks

LAB Control Signals

Each LAB contains dedicated logic for driving a maximum of 10 control signals to its ALMs at a time. Control signals include three clocks, three clock enables, two asynchronous clears, a synchronous clear, and synchronous load control signals.

Although you generally use synchronous-load and clear signals when implementing counters, you can also use them with other functions. Each LAB has two unique clock sources and three clock enable signals, as shown in Figure2–4. The LAB control block can generate up to three clocks using two clock sources and three clock enable signals. Each clock and clock enable signals are linked. For example, any ALM in a particular LAB using the labclk1 signal also uses the labclkena1 signal. If the LAB uses both the rising and falling edges of a clock, it also uses two LAB-wide clock signals.

De-asserting the clock enable signal turns off the corresponding LAB-wide clock. The LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control signals. In addition to data, the inherent low skew of the MultiTrack interconnect allows clock and control signal distribution.

Figure2–4.LAB-Wide Control Signals

There are two uniqueclock signals per LAB.Dedicated Row LAB Clocks666Local Interconnect

Local Interconnect

Local Interconnect

Local Interconnect

Local Interconnect

Local Interconnect

labclk0labclkena0or asyncloador labpresetlabclk1labclkena1

labclk2labclkena2

syncloadlabclr0

labclr1synclr

Arria II Device Handbook Volume 1: Device Interfaces and Integration

Chapter 2:Logic Array Blocks and Adaptive Logic Modules in ArriaII DevicesAdaptive Logic Modules

Figure2–5.High-Level Block Diagram of the ArriaII ALM

shared_arith_incarry_inreg_chain_inlabclkTo general orlocal routing6-Input LUTCombinational/Memory ALUT0dataf0datae0dataadatabdatacdataddatae1dataf16-Input LUTadder0DQTo general orlocal routingreg0adder1DQTo general orlocal routingreg1To general orlocal routingCombinational/Memory ALUT1reg_chain_outshared_arith_outcarry_outArria II Device Handbook Volume 1: Device Interfaces and Integration

FPGA可编程逻辑器件芯片EP2AGX95EF29C5N中文规格书 - 图文

AIIGX51002-2.0Thischapterdescribesthefeaturesofthelogicarrayblock(LAB)intheArria?IIcorefabric.TheLABiscomposedofbasicbuildingblocksknownasadaptivelogicmodules(AL
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