Data Sheet
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM1410/ADuM1411/ADuM1412 digital isolators require no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 16). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for VDD1, and between Pin 15 and Pin 16 for VDD2. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless both ground pins on each package are connected together close to the package.
VDD1GND1VIAVIBVICVIDDISABLEGND1VDD2GND2VOAVOBVOCVODCTRL2GND2ADuM1410/ADuM1411/ADuM1412
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder using the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than approximately 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 14) by the watchdog timer circuit.
The magnetic field immunity of the ADuM1410/ADuM1411/ ADuM1412 is determined by the changing magnetic field, which induces a voltage in the transformer’s receiving coil large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM1410/ADuM1411/ADuM1412 is examined because it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by
V = (?dβ/dt) ∑ π rn2; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm). N is the number of turns in the receiving coil.
100MAXIMUM ALLOWABLE MAGNETIC FLUXDENSITY (kgauss)ADuM1410Figure 16. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, it is important to minimize board coupling across the isolation barrier. Furthermore, users should design the board layout so that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The input-to-output propagation delay time for a high-to-low transition may differ from the propagation delay time of a low-to-high transition.
INPUT (VIx)50580-016101tPLHOUTPUT (VOx)tPHL50580-0170.1Figure 17. Propagation Delay Parameters
0.0110k100k1M10M100MRev. M | Page of 22
06580-0180.0011kData Sheet
VDD11GND1*2VIA3VIB4VOC5VOD6CTRL17GND1*81615ADuM1410/ADuM1411/ADuM1412
VDD2GND2*VOAVOBVICVIDCTRL2GND2*06580-006ADuM1412TOP VIEW(Not to Scale)14131211109*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTHTO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLYCONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.Figure 7. ADuM1412 Pin Configuration
Table 13. ADuM1412 Pin Function Descriptions
Pin No. Mnemonic 1 VDD1 2 GND1 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VIA VIB VOC VOD CTRL1 GND1 GND2 CTRL2 VID VIC VOB VOA GND2 VDD2
Description
Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. Logic Input A. Logic Input B. Logic Output C. Logic Output D.
Default Output Control. Controls the logic state the outputs assume when the input power is off. VOC and VOD
outputs are high when CTRL1 is high or disconnected and VDD2 is off. VOC and VOD outputs are low when CTRL1 is low and VDD2 is off. When VDD2 power is on, this pin has no effect.
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended.
Default Output Control. Controls the logic state the outputs assume when the input power is off. VOA and VOB
outputs are high when CTRL2 is high or disconnected and VDD1 is off. VOA and VOB outputs are low when CTRL2 is low and VDD1 is off. When VDD1 power is on, this pin has no effect. Logic Input D. Logic Input C. Logic Output B. Logic Output A.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended.
Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).
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ADuM1410/ADuM1411/ADuM1412 Data Sheet
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Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
2.0108CURRENT/CHANNEL (mA)ADuM1410/ADuM1411/ADuM1412
1.5CURRENT (mA)61.05V45V3V0.523V06580-0080246DATA RATE (Mbps)8100246DATA RATE (Mbps)810Figure 8. Typical Supply Current per Input Channel vs. Data Rate
for 5 V and 3 V Operation
1.00.90.8CURRENT/CHANNEL (mA)Figure 11. Typical ADuM1410 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
1080.70.60.50.40.30.20.106580-009CURRENT (mA)5V643V25V3V0246DATA RATE (Mbps)8100246DATA RATE (Mbps)81006580-01206580-01300Figure 9. Typical Supply Current per Output Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
1.41.2Figure 12. Typical ADuM1410 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
108CURRENT/CHANNEL (mA)1.0CURRENT (mA)0.85V0.60.43V0.200246DATA RATE (Mbps)810645V23V00246DATA RATE (Mbps)810Figure 10. Typical Supply Current per Output Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
06580-010Figure 13. Typical ADuM1411 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
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06580-01100ADuM1410/ADuM1411/ADuM1412
1010Data Sheet
88CURRENT (mA)CURRENT (mA)6645V23V45V23V06580-0140246DATA RATE (Mbps)8100246DATA RATE (Mbps)810Figure 14. Typical ADuM1411 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation Figure 15. Typical ADuM1412 VDD1 or VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
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06580-01500
MEMORY存储芯片ADM708TARZ-REEL中文规格书 - 图文
