Master SPI Dual (x2) and Quad (x4) Read Commands
The Master SPI configuration mode in Spartan-6 FPGAs supports the SPI flash memory dual (x2) and quad bit (x4) memory fast output read commands. To enable this
configuration method in software, the BitGen spi_buswidth option is used to create a .bit file for SPI x2 or x4. The FPGA still initially boots in x1 mode and then switches to x2 or x4 mode.
In x2 mode, the Fast-Read Dual Output (3Bh) instruction is issued and is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins, DO and DIO (MOSI), instead of just DO. This allows data to be transferred from the dual output at twice the rate of standard SPI devices. The timing diagram of the Master Serial SPI configuration mode using an SPI flash with dual read-bit command (3Bh) is shown in Figure2-17.
X-Ref Target - Figure 2-17CSO_BCCLKMOSI/MISO[0]DIN/MISO[1]Read Command24-Bit AddressDummyByte (8 Bits)D6D4D2D0D7D5D3D1Data Byte 1UG380_c2_17_052009Figure 2-17:Timing Diagram of SPI Dual-Read Bit Command (3Bh)
In x4 mode, the Fast-Read Quad Output (6Bh) instruction is issued and is similar to the standard Fast Read (0Bh) instruction except that data is output on four data pins, instead of just DO. This allows data to be transferred from the quad output at four times the rate of standard SPI devices. The timing diagram of the Master Serial SPI configuration mode using an SPI flash with quad read bit command (6Bh) is shown in Figure2-18.
X-Ref Target - Figure 2-18CSO_BCCLKMOSI/MISO[0]DIN/MISO[1]MISO[2]MISO[3]D0–D7 Next D0–D7 Read Command24-Bit AddressDummyByte (8 Bits)D4D0D4D0D5D1D5D1D6D2D6D2D7D3D7D3Data Byte 1 This corresponds with the first two columns of data.Data Byte 2 This corresponds with the last two columns of data.UG380_c2_18_052009Figure 2-18:Timing Diagram of SPI Quad-Read Bit Command (6Bh)
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
Master BPI Configuration Interface
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
Chapter 2:Configuration Interface Basics
Figure2-21 shows the BPI configuration waveforms.
X-Ref Target - Figure 2-21CCLKINIT_BFCS_BFOE_BFWE_BA[n:0]D[n:0]DONEUG380_c2_20_05210901D02D13D2D3nDnFigure 2-21:Spartan-6 FPGA BPI Configuration Waveforms
Notes related to Figure2-21:1.
CCLK is output in BPI modes. The parallel NOR flash does not require CCLK, but theSpartan-6 FPGA uses the rising edge of CCLK to sample D[n:0] pins. The falling edgeof CCLK is used to generate the address outputs.
The Spartan-6 FPGA stops loading the bitstream after the DONE pin goes High.Dual-purpose configuration I/O switches to User mode after the GTS_cycle. Bydefault, this is one cycle after DONE goes High.
In D[n:0], n can be 7 or 15. For A[n:0], n can be a value up to 25.
FCS_B, FOE_B, and FWE_B should have weak pull-ups after configuration througheither I/O constraints or external pull-up resistors.
The first address 0 for Master BPI is extended for multiple cycles due to the initiallatency.
2.3.4.5.6.
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2024
Master BPI Configuration Interface
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
Boundary-Scan for Spartan-6 Devices Using IEEE Std 1149.1
Using Boundary-Scan in Spartan-6 Devices
For single-device configuration, the TAP controller commands are issued automatically if the part is being configured with Xilinx? iMPACT software. The download cable must be attached to the appropriate four JTAG pins (TMS, TCK, TDI, and TDO) to deliver the bitstream automatically from the computer port to the Spartan-6 FPGA. The iMPACT software automatically checks for proper connections and drives the commands to deliver and/or verify that the configuration bits are properly managed.
Figure3-2 shows a typical JTAG setup with the simple connection required to attach a single device to a JTAG signal header, which can be driven from a processor or a Xilinx programming cable under control of iMPACT software. TCK is the clock used for
boundary-scan operations. The TDO-TDI connections create a serial datapath for shifting data through the JTAG chain. TMS controls the transition between states in the TAP
controller; see Chapter10, Advanced JTAG Configurations. Proper physical connections of all of these signals are essential to JTAG functionality.
X-Ref Target - Figure 3-2JTAG HeaderSpartan-6 FPGATDOTDITMSTCKTDITMSTCKDeviceUG380_c3_02_042909TDOFigure 3-2:Single-Device JTAG Programming Connections
Multiple Device Configuration
It is possible to configure multiple Spartan-6 devices in a chain. (See Figure3-3.)
X-Ref Target - Figure 3-3JTAG HeaderTDOSpartan-6FPGATDITMSTCKTDITMSTCKPROGRAM_BTDOSpartan-6FPGATDITMSTCKPROGRAM_BTDOSpartan-6FPGATDITMSTCKPROGRAM_BTDODevice 0Device 1Device 2UG380_c3_03_042909Figure 3-3:Boundary-Scan Chain of Devices
If JTAG is the only configuration mode, then PROGRAM_B, INIT_B, and DONE can be tied High to a 330Ω resistor.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
FPGA可编程逻辑器件芯片XC2S100-5TQG144I中文规格书 - 图文
