1.2 GHz CMOS全集成锁相环的设计
赵坤;满家汉;叶青;叶甜春
【期刊名称】《电子器件》 【年(卷),期】2006(029)002
【摘要】On the base of analyzing the factors affecting the performance of the PLL, the corresponding scheme for optimization is presented and a 1.2 GHz LC phase-locked loop (PLL) is designed. The circuit design of the PLL that consists of a LC-tank circuit, prescaler, frequency divider, phase/frequency detector, charge pump that includes a bandgap current reference and a passive loop filter is introduced and the simulation results are given. The PLL is designed in SMIC 0.18 μm 3.3 V 1P6M CMOS RF technology and the passive loop filter is also on-chip and no off-chip components are needed.%在分析影响锁相环性能的各种因素的基础上,采用相应的优化方法设计了一款全集成的1.2 GHz LC锁相环.详细介绍了该锁相环中各模块电路(包括LC型压控振荡器,预分频器,分频器,鉴频/鉴相器,含有带隙基准电流源的电荷泵以及片上无源滤波器等)的设计,并且给出了仿真结果.该锁相环采用SMIC 0.18 μm RF CMOS工艺设计实现,其中无源滤波器也集成在片上,实现了完全片上集成. 【总页数】4页(314-317)
【关键词】锁相环;压控振荡器;预分频器;电荷泵;带隙基准电流源 【作者】赵坤;满家汉;叶青;叶甜春
【作者单位】中国科学院微电子研究所,北京,100029;中国科学院微电子研究所,
1.2 GHz CMOS全集成锁相环的设计
