Chapter4
User Primitives
The configuration primitives described in this chapter are provided for users to access FPGA configuration resources during or after FPGA configuration. For additional
information and instantiation templates, refer to UG615, Spartan-6 Libraries Guide for HDL Designs.
BSCAN_SPARTAN6
JTAG is a standard four-pin interface: TCK, TMS, TDI, and TDO. Many applications are built around this interface. The JTAG TAP controller is a dedicated state machine inside the configuration logic. BSCAN_SPARTAN6 provides access between the JTAG TAP controller and user logic in fabric. There are up to four instances of BSCAN_SPARTAN6 for each device. Each instance of this design element can handle one JTAG USER instruction
(USER1 through USER4) as set with the JTAG_CHAIN attribute. To handle all four USER instructions, four of these elements can be instantiated, and the JTAG_CHAIN attribute must be set appropriately. Table4-1 lists the BSCAN_SPARTAN6 port descriptions. Table 4-1:BSCAN_SPARTAN6 Port DescriptionsSignal Name SEL
TypeOutput
Function
Active-High interface selection output. SEL=1 when the JTAG instruction register holds the corresponding (USER1, USER2, USER3, or USER4) instruction. Change in Update_IR state. SEL changes on the falling edge of TCK in the UPDATE_IR state of the TAP controller.
Active-High reset output. RESET=1 during the TEST-LOGIC-RESET state, PROGRAM_B, or during
power-up. This signal is deasserted on the falling edge of TCK.Fed through directly from the FPGA TDI pin.
DRCK is the same as TCK in the Capture_DR and Shift_DR states. If the interface is not selected by the instruction register, DRCK remains High.
Active-High pulse indicating the Capture_DR state. This signal is asserted on the falling edge of TCK.
Active-High pulse indicating the Update_DR state. This signal is asserted on the falling edge of TCK.
Active-High pulse indicating the Shift_DR state. This signal is asserted on the falling edge of TCK. Indicates JTAG is in Run Test/Idle state.
RESETOutput
TDIDRCK
OutputOutput
CAPTUREUPDATESHIFTRUNTEST
OutputOutputOutputOutput
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 4:User Primitives
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Generating PROM Files
Parallel Bus Bit Order
Traditionally, in SelectMAP x8 mode, configuration data is loaded one byte per CCLK, with the most-significant bit (MSB) of each byte presented to the D0 pin. Although this convention (D0 = MSB, D7 = LSB) differs from many other devices, it is consistent across all Xilinx FPGAs. The bit-swap rule also applies to Spartan-6 FPGA BPI x8 modes (see Bit Swapping, page80).
In Spartan-6 devices, the bit-swap rule is extended to x16 bus widths; the data is bit swapped within each byte.
Table5-8 and Table5-9 show examples of a sync word inside a bitstream. These examples illustrate what is expected at the FPGA data pins when using parallel configuration modes, such as Slave SelectMAP and Master SelectMAP (BPI) modes.Table 5-8:Sync Word Bit Swap Example
Sync Word
Bitstream FormatBit Swapped
Notes:
1.[31:24] changes from 0xAA to 0x55 after bit swapping.
[31:24](1)0xAA0x55
[23:16]0x990x99
[15:8]0x550xAA
[7:0]0x660x66
Table 5-9:Sync Word Data Sequence Example for x8 and x16 Modes
CCLK CycleD[7:0] pins for x8 D[15:0] pins for x16
10x550x5599
20x990xAA66
30xAA
40x66
Delaying Configuration
There are two ways to delay configuration for Spartan-6 devices:??
Table 5-10:
Hold the INIT_B pin Low during initialization. When INIT_B has gone High,configuration cannot be delayed by subsequently pulling INIT_B Low.
Hold the PROGRAM_B pin Low. The signals relating to initialization and delayingconfiguration are defined in Table5-10.
Access(1)
Externally accessible via the PROGRAM_B pin.
Signals Relating to Initialization and Delaying Configuration
TypeInput
Description
Global asynchronous chip reset. Can be held Low to delay configuration.
Before the Mode pins are sampled, INIT_B is an input that can be held Low to delay configuration.
After the Mode pins are sampled, INIT_B is an open-drain, active-Low output that indicates whether a CRC error occurred during configuration or a readback CRC error occurred after configuration (when enabled):0 = CRC error
1 = No CRC error (needs an external pull-up)
Signal NamePROGRAM_BINIT_B
Input, Externally accessible via the Output, INIT_B pin.or Open Drain
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
FPGA可编程逻辑器件芯片XC2V6000-6BG575I中文规格书
