Thermal Specifications
Summary
This chapter provides thermal data associated with Virtex?-5 FPGA packages. The following topics are discussed:?????
Introduction
Power Management StrategySome Thermal Management OptionsSupport for Compact Thermal Models (CTM)References
Introduction
Virtex-5 devices are offered exclusively in thermally efficient flip-chip BGA packages. These 1.0 mm flip-chip packages range in pin-count from the smaller 19x19mm FF324 to the 42.5x42.5mm FF1760. The suite of packages is used to address the various power requirements of the Virtex-5 devices. All Virtex-5 devices are implemented in the 65nm process technology
Similar to Virtex-4 FPGAs, all Virtex-5 devices feature versatile SelectIO? resources that support a variety of I/O standards. They also include Digital Clock Managers (DCMs), DSPs, and other traditional features and blocks (such as block RAM) contained in earlier Virtex products.
In line with Moore's law, the transistor count in this family of devices has been increased substantially. Though several innovative features at the silicon level have been deployed to minimize power dissipation, including leakage at the 65nm node, these products have more densely packed transistors and embedded blocks with the capability to run faster than before. Thus, a fully configured Virtex-5 design that exploits the fabric speed and incorporates several embedded circuits and systems can present power consumption challenges that must be managed.
Unlike features in an ASIC or a microprocessor, the combination of FPGA features used in an user application are not known to the component supplier. Therefore, it remains a challenge for Xilinx to predict the power requirements of a given FPGA when it leaves the factory. Accurate estimates are obtained when the board design takes shape. For this purpose, Xilinx offers and supports a suite of integrated device power analysis tools to help users quickly and accurately estimate their design power requirements. Virtex-5 devices are supported similarly to previous FPGA products. The uncertainty of design power requirements makes it difficult to apply canned thermal solutions to fit all users. Therefore, Xilinx devices do not come with preset thermal solutions. The user’s operating conditions dictate the appropriate solution.
Virtex-5 FPGA Packaging and Pinout Specification
Power Management Strategy
?Heat Sinking Solutions at the System Level
Depending on the system's physical as well as mechanical constraints, the expectationis that the thermal budget is maintained with custom or OEM heat sink solutions,providing the third prong in the thermal management strategy. At this point, Xilinxhas left the heat sink solution to the system-level designers who can tailor the designand solution to the constraints of their systems, being fully aware that the part hascertain inherent capabilities for delivering the heat to the surface.
Heat sink solutions do exist and can be effective on these low θJB flip-chip platforms.Table6-3 below illustrates a finned heat sink solution matrix in Network environment(1U and 2U) arrangement for 35mm packages and up for power ranging from 15W to40W. The AAVID standard finned heat sink offerings are used to illustrate the coverage given thermal budgets of ΔT=35°C and ΔT=45°C scenarios. Other heat sinkconfigurations can be explored similarly.
Table 6-3:Finned Heat Sink Solution Matrix for Large Flip-chip BGA in NetworkPackage Power
(W)
1U(5)2U(6)1U(5)2U(6)1U(5)2U(6)1U(5)2U(6)
Note4 Note2 Note4 Note4
35 x 35 mm
FF1136/FF1153/FF1156ΔT=35°C
Note 1Note 1
Note2 Note1 Note3 Note2––
Note4 Note2 Note4 Note4
Note 4Note 3
ΔT=45°C
42.5 x 42.5 mm
FF1738/FF1759/FF1760ΔT=35°C
Note 1Note 1
Note2 Note1 Note3 Note2
Note 3Note 2ΔT=45°C
15W
25W
35W
40W
Notes:
1.
2.3.4.5.6.
Solution available at 200 LFM, for example, AAVID finned part number 68520, 72390, 72415.Solution available at 400 LFM, for example, AAVID finned part number 68520, 69920.
Solution available at 600 LFM, for example, AAVID finned part number 72390, 69920, 74590.No standard. AAVID finned solution below 600 LFM—custom finned might be required.For 1U Height—(max heat sink height = 26mm)For 2U Height—(max heat sink height = 64mm
The Virtex-5 FPGA packages can be grouped into medium- and high-performance
packages based on their power handling capabilities. All Virtex-5 FPGA packages can use thermal enhancements, ranging from simple airflow to schemes that can include passive as well as active heat sinks. This is particularly true for the bigger flip-chip BGA packages where system designers have the option to further enhance the packages with bigger and more elaborate heat sinks to handle excesses of 25W with arrangements that consider system –physical constraints as illustrated in Table6-3.
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 6:Thermal Specifications
The flip-chip thermal management chart in Figure6-2 illustrates simple but incremental power management schemes that can be applied on a flip-chip BGA package.
X-Ref Target - Figure 6-2Low End1–6WBare Package withModerate Air8–12°C/WBare PackagePackage can beused with moderateairflow within a systemMid RangePassive H/S + Air 4–10W5–10°C/WPackaged Used withVarious Forms ofPassive Heat SinksHeat spreader techniquesHigh End8–25WActive Heat Sink 2–3°C/W or BetterPackage Used withActive Heat SinksTEC and board levelheat spreader techniquesUG195_c5_02_101006 Virtex-5 FPGA Packaging and Pinout Specification
Chapter 4:Mechanical Drawings
FF665, FFG665, EF665, FFV665 Flip-Chip Fine-Pitch
BGA Package Specifications (1.00mm Pitch)
X-Ref Target - Figure 4-3ug195_c4_ff/ffg/ef/ffv665_042518Figure 4-3: FF665, FFG665, EF665, FFV665 Flip-Chip Fine-Pitch BGA Package Specifications
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 4:Mechanical Drawings
EF1738 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm Pitch)
X-Ref Target - Figure 4-9ug195_c4_21_101110Figure 4-9:EF1738 Flip-Chip Fine-Pitch BGA Package Specifications
Virtex-5 FPGA Packaging and Pinout Specification
FPGA可编程逻辑器件芯片XC6VLX365T-2FFG1156C中文规格书 - 图文
