Cascading PLLs
You can cascade the corner and center PLLs through the GCLK and RCLK networks (ArriaIIGX devices) or left/right and top/bottom PLLs through the GCLK and
RCLK networks (Arria II GZ devices). In addition, where two PLLs exist next to each other, there is a direct connection between them that does not require the GCLK and RCLK network. By cascading PLLs, you can use this path to reduce clock jitter. For ArriaII GX devices, the direct PLL cascading feature is available in PLL_5 and PLL_6 on the right side of EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices. ArriaII GX devices allow cascading of PLL_1 and PLL_4 to the transceiver PLLs (clock management unit PLLs and receiver clock data recoveries [CDRs]). ArriaIIGZ
devices allows cascading the left and right PLLs to transceiver PLLs (CMU PLLs and receiver CDRs).
If your design cascades PLLs, the source (upstream) PLL must have a low-bandwidth setting, while the destination (downstream) PLL must have a high-bandwidth setting. Ensure that there is no overlap of the bandwidth ranges of the two PLLs.
fFor more information, refer to the “FPGA Fabric PLLs-Transceiver PLLs Cascading”
section in the Transceiver Clocking in Arria II Devices chapter.fFor more information about PLL cascading in external memory interfaces designs,
refer to the External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide.
PLLs in ArriaII Devices
ArriaII GX devices offer up to six PLLs per device and seven outputs per PLL, while ArriaII GZ devices offer up to eight PLLs that provide robust clock management and synthesis for device clock management, external system clock management, and
high-speed I/O interfaces. The nomenclature for the PLLs follows their geographical location in the device floor plan. For the location and number of PLLs in ArriaII devices, refer to Figure5–1 on page5–4 through Figure5–4 on page5–6.
1
Depending on the package, ArriaIIGX devices offer up to eight transceiver
transmitter (TX) PLLs per device that can be used by the FPGA fabric if they are not used by the transceiver.
fFor more information about the number of general-purpose and transceiver TX PLLs
in each device density, refer to the Overview for Arria II Device Family chapter. For more information about using the transceiver TX PLLs in the transceiver block, refer to the Transceiver Clocking in Arria II Devices chapter.
All ArriaII PLLs have the same core analog structure and support features with minor differences in the features that are supported for ArriaII GZ devices.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 5:Clock Networks and PLLs in Arria II Devices
PLLs in ArriaII Devices
Table5–13 lists the PLL features in ArriaII devices.
Table5–13.PLL Features in Arria II Devices
Feature
C (output) countersM, N, C counter sizesDedicated clock outputs
ArriaII GX PLLs
Top/Bottom PLLs
71 to 512
1 single-ended or 1 differential
pair
3 single-ended or 3 differential
pairs (1), (2)4 single-ended or 2 differential
pin pairs
NoYes (3)
Through GCLK and RCLK and dedicated path between adjacent PLLs. Cascading between the general-purpose PLL and transceiver PLL is supported in PLL_1 and
PLL_4.All except external feedback
mode when you use differential I/Os
YesYes
Down to 96.125ps (5)
Yes YesYes
101 to 5126 single-ended or 4single-ended and 1differential pair4 single-ended or 2 differential pin pairsSingle-ended or differential
Yes (3)
Arria II GZ PLLs
Left/Right PLLs
71 to 512
2 single-ended or 1 differential
pair4 single-ended or 2 differential
pin pairs
Single-ended only
Yes (3)
Clock input pins
External feedback input pinSpread-spectrum input clock tracking
PLL cascading
Through GCLK and RCLK and a dedicated path between adjacent PLLsThrough GCLK and RCLK and dedicated path between adjacent PLLs (4)
Compensation modesPLL drives DIFFCLK and LOADENVCO output drives DPA clockPhase shift resolutionProgrammable duty cycleOutput counter cascadingInput clock switchover
Notes to Table5–13:
All except LVDS clock network compensation
NoNo
Down to 96.125ps (5)
Yes YesYes
All except external feedback
mode when you use differential I/Os
YesYes
Down to 96.125ps (5)
Yes YesYes
(1)PLL_5 and PLL_6 do not have dedicated clock outputs.
(2)The same PLL clock output drives three single-ended or three differential I/O pairs. This is only supported in PLL_1 and PLL_3 of EP2AGX95,
EP2AGX125, EP2AGX190, and EP2AGX260 devices.(3)This is applicable only if the input clock jitter is within the input jitter tolerance specifications.(4)The dedicated path between adjacent PLLs is not available on L1, L4, R1, and R4 PLLs.
(5)The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For degree increments, the ArriaII device
can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and C countervalue.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 5:Clock Networks and PLLs in Arria II DevicesPLLs in ArriaII Devices
PLL Hardware Overview in Arria II Devices
Figure5–20 shows a simplified block diagram of the major components of the ArriaIIPLL.
Figure5–20.PLL Block Diagram for Arria II Devices
To DPA block onLeft/Right PLLspfdena4inclk0ClockSwitchoverBlock÷nclkswitchclkbad0clkbad1activeclockPFDLockCircuitlockedCasade outputto adjacent PLL /2, /48÷2(2)88÷C0GCLKs÷C1PLL Output MuxDedicatedclock inputsCPLFVCORCLKsExternal clockoutputsDIFFIOCLK fromLeft/Right PLLsLOAD_EN fromLeft/Right PLLsFBOUT (3)Externalmemoryinterface DLL÷C2÷C3GCLK/RCLKinclk1Cascade inputfrom adjacent PLL÷Cn÷m(1)no compensation modeZDB, External feedback modesLVDS Compensation modeSource Synchronous, normal modesFBINDIFFIOCLK networkGCLK/RCLK networkNotes to Figure5–20:
(1)The number of post-scale counters is seven for left and right PLLs and ten for top and bottom PLLs.(2)This is the VCO post-scale counter K.
(3)The FBOUT port is fed by the M counter in Arria II PLLs. The FBOUT port is only available in ArriaIIGZ devices.
1
You can drive the GCLK or RCLK clock input with an output from another PLL, a pin-driven GCLK or RCLK, or through a clock control block, provided the clock
control block is fed by an output from another PLL, or a pin driven dedicated GCLK or RCLK. An internally-generated global signal or general purpose I/O (GPIO) pin cannot drive the PLL.
PLL Clock I/O Pins
For ArriaII GX devices, each PLL supports one of the following clock I/O pin configurations:
■■
One single-ended I/O or one differential I/O pair.
Three single-ended I/O or three differential I/O pairs (this is only supported inPLL_1 and PLL_3 of EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260
devices). You can only access one differential I/O pair or one single-ended pin at atime.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 5:Clock Networks and PLLs in Arria II Devices
PLLs in ArriaII Devices
Figure5–21 shows the clock I/O pins associated with ArriaII GX PLLs.
Figure5–21.External Clock Outputs for Arria II GX PLLs
Internal LogicC0C1C2Arria II GX PLLsC3C4C5C6mclkena0 (3)clkena1(3)PLL<#>_CLKOUT<#>p (1), (2)PLL<#>_CLKOUT<#>n (1), (2)Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 5:Clock Networks and PLLs in Arria II DevicesPLLs in ArriaII Devices
Arria II Device Handbook Volume 1: Device Interfaces and Integration
FPGA可编程逻辑器件芯片EP2AGX95EF35I5N中文规格书 - 图文
