Asynchronous Interface Bus Operation
The bus on the device is multiplexed. Data I/O, addresses, and commands all share thesame pins. I/O[15:8] are used only for data in the x16 configuration. Addresses andcommands are always supplied on I/O[7:0].
The command sequence typically consists of a COMMAND LATCH cycle, address inputcycles, and one or more data cycles, either READ or WRITE.
Table 6: Asynchronous Interface Mode Selection
Mode1Standby2Command inputAddress inputData inputData outputWrite protectNotes:
CE#HLLLLXCLEXHLLLXALEXLHLLXHXXWE#XRE#XHHHI/OxXXXXXXWP#0V/VCCHHHXL1.Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH
or VIL.
2.WP# should be biased to CMOS LOW or HIGH for standby.
Asynchronous Enable/Standby
When the device is not performing an operation, the CE# pin is typically driven HIGHand the device enters standby mode. The memory will enter standby if CE# goes HIGHwhile data is being transferred and the device is not busy. This helps reduce power con-sumption.
The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn-chronous memory bus as other Flash or SRAM devices. Other devices on the memorybus can then be accessed while the NAND Flash is busy with internal operations. Thiscapability is important for designs that require multiple NAND Flash devices on thesame bus.
A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signalsignifies that an ADDRESS INPUT cycle is occurring.
Asynchronous Commands
An asynchronous command is written from I/O[7:0] to the command register on the ris-ing edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, somecommands, including READ STATUS (70h) and READ STATUS ENHANCED (78h), areaccepted by die (LUNs) even when they are busy.
For devices with a x16 interface, I/O[15:8] must be written with zeros when a commandis issued.
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m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Command Definitions
Table 7: Command Set (Continued)
Number ofValidAddressCycles5DataInputCyclesOptionalValid WhileCommandSelected LUNCycle #2is Busy110hNoValid WhileOther LUNsare Busy2YesCommandPROGRAM FOR INTER-NAL DATA MOVEBlock Lock OperationsBLOCK UNLOCK LOWBLOCK UNLOCK HIGHBLOCK LOCKBLOCK LOCK-TIGHTBLOCK LOCK READSTATUSOTP DATA LOCK BYPAGE (ONFI)OTP DATA PROGRAM(ONFI)OTP DATA READ (ONFI)CommandCycle #185hNotes23h24h2Ah2Ch7Ah33––3––––––––––NoNoNoNoNoYesYesYesYesYesOne-Time Programmable (OTP) Operations80h80h00h555NoYesNo10h10h30hNoNoNoNoNoNo777Notes:
1.Busy means RDY = 0.
2.These commands can be used for interleaved die (multi-LUN) operations (see Interleaved
Die (Multi-LUN) Operations (page 106)).
3.Do not cross plane address boundaries when using READ for INTERNAL DATA MOVE and
PROGRAM for INTERNAL DATA MOVE.
4.These commands supported only with ECC disabled.
5.Issuing a READ PAGE CACHE series (31h, 00h-31h, 3Fh) command when the array is busy
(RDY = 1, ARDY = 0) is supported if the previous command was a READ PAGE (00h-30h)or READ PAGE CACHE series command; otherwise, it is prohibited.
6.Issuing a PROGRAM PAGE CACHE (80h-15h) command when the array is busy (RDY = 1,
ARDY = 0) is supported if the previous command was a PROGRAM PAGE CACHE(80h-15h) command; otherwise, it is prohibited.
7.OTP commands can be entered only after issuing the SET FEATURES command with the
feature address.
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m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
READ ID Parameter Tables
Table 9: READ ID Parameters for Address 00h (Continued)
b = binary; h = hexadecimalOptionsSerial access(MIN)Byte value1.8V3.3V25ns20nsMT29F4G08ABADAMT29F4G16ABADAMT29F4G08ABBDAMT29F4G16ABBDAMT29F8G08ADBDAMT29F8G16ADBDAMT29F8G08ADADAMT29F8G16ADADAMT29F16G08AJADAByte 4Internal ECC level4-bit ECC/512 (main) +4 (spare) + 8 (parity)bytes24Plane sizeInternal ECCByte value2GbECC disabledECC enabledMT29F4G08ABADAMT29F4G16ABADAMT29F4G08ABBDAMT29F4G16ABBDAMT29F8G08ADBDAMT29F8G16ADBDAMT29F8G08ADADAMT29F8G16ADADAMT29F16G08AJADA0100000000011111111100000000011111111100001111111110000011111111100000000010101101010bI/0701110000111010101010000000000111111111I/06I/05I/04I/0300000000000111111111000000000111111111I/02I/01I/00Value0xxx0b1xxx0b95hD5h15h55h15h55h95hD5h95hPlanes per CE#01b10b101b0b1b56h56h56h56h5Ah5Ah5Ah5Ah5AhPDF: 09005aef83b25735
m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Parameter Page Data Structure Tables
Table 11: Parameter Page Data Structure (Continued)
Byte44–63DescriptionDevice modelMT29F4G08ABBDAH4MT29F4G08ABBDAHCMT29F4G16ABBDAHCMT29F4G16ABBDAH4MT29F8G08ADBDAH4MT29F8G16ADBDAH4MT29F4G08ABADAWPMT29F4G08ABADAH4MT29F4G16ABADAWPMT29F4G16ABADAH4MT29F8G08ADADAH4MT29F8G16ADADAH4MT29F16G08AJADAWP6465–6667–7980–8384–8586–8990–9192–9596–99Manufacturer IDDate codeReservedNumber of data bytes per pageNumber of spare bytes per pageNumber of data bytes per partial pageNumber of spare bytes per partial pageNumber of pages per blockNumber of blocks per unitValue4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h,42h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h,42h, 44h, 41h, 48h, 43h, 20h, 20h, 20h, 20h4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h,42h, 44h, 41h, 48h, 43h, 20h, 20h, 20h, 20h4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h,42h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 44h,42h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 31h, 36h, 41h, 44h,42h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h,41h, 44h, 41h, 57h, 50h, 20h, 20h, 20h, 204Dh, 54h, 32h, 39h, 46h, 34h, 47h, 30h, 38h, 41h, 42h,41h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h,41h, 44h, 41h, 57h, 50h, 20h, 20h, 20h, 20h4Dh, 54h, 32h, 39h, 46h, 34h, 47h, 31h, 36h, 41h, 42h,41h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 44h,41h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h4Dh, 54h, 32h, 39h, 46h, 38h, 47h, 31h, 36h, 41h, 44h,41h, 44h, 41h, 48h, 34h, 20h, 20h, 20h, 20h4Dh, 54h, 32h, 39h, 46h, 31h, 36h, 47h, 30h, 38h, 41h,4Ah, 41h, 44h, 41h, 57h, 50h, 20h, 20h, 20h2Ch00h, 00h00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h00h, 08h, 00h, 00h40h, 00h00h, 02h, 00h, 00h10h, 00h40h, 00h, 00h, 00h00h, 10h, 00h, 00hPDF: 09005aef83b25735
m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
4Gb, 8Gb, 16Gb: x8, x16 NAND Flash Memory
Parameter Page Data Structure Tables
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m60a_4gb_ecc_nand.pdf – Rev. M 2/12 EN
FPGA可编程逻辑器件芯片EP1S20F780I7N中文规格书 - 图文
