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ATmega16A

1. Pin Configurations

Figure 1-1.

Pinout ATmega16A

PDIP

(XCK/T0) PB0

PA0 (ADC0) (T1) PB1 PA1 (ADC1) (INT2/AIN0) PB2 PA2 (ADC2) (OC0/AIN1) PB3

PA3 (ADC3) (SS) PB4 PA4 (ADC4) (MOSI) PB5 PA5 (ADC5) (MISO) PB6 PA6 (ADC6) (SCK) PB7 PA7 (ADC7)RESET AREFVCC GND GND AVCC

XTAL2 PC7 (TOSC2) XTAL1 PC6 (TOSC1) (RXD) PD0 PC5 (TDI) (TXD) PD1 PC4 (TDO) (INT0) PD2 PC3 (TMS) (INT1) PD3 PC2 (TCK) (OC1B) PD4 PC1 (SDA)(OC1A) PD5 PC0 (SCL)(ICP1) PD6

PD7 (OC2)

TQFP/QFN/MLF

)) 02CT ) ON0 I//T))))/0123 10 ))KCCC CSNNII1CSAADDDDTX A ((((( AAA 43210DC((((3BBBBBNC012AAAA PPPPPGVPPP P

(MOSI) PB5 PA4 (ADC4) (MISO) PB6 PA5 (ADC5) (SCK) PB7 PA6 (ADC6) RESET PA7 (ADC7)VCC AREFGND GND XTAL2 AVCC

XTAL1 PC7 (TOSC2)(RXD) PD0 PC6 (TOSC1)(TXD) PD1 PC5 (TDI) (INT0) PD2

PC4 (TDO)

34567NOTE:

DDDDDCD 123PPPPPCN0Bottom pad shouldVGCCCC PPPP)))))))))be soldered to ground.

12LTBA1 N11PCCAKSSDCICCCO(OOI(STM((((T(((

8154BS–AVR–07/09

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ATmega16A

2. Overview

The ATmega16A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

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ATmega16A

2.1

Block Diagram

Figure 2-1.

Block Diagram

PC7

VCC

PA0 - PA7

PC0 -

PORTA DRIVERS/BUFFERS

PORTC DRIVERS/BUFFERS

GND

PORTA DIGITAL INTERFACE

PORTC DIGITAL INTERFACE

AVCC

MUX &ADC

ADC

INTERFACE

TWI AREF

PROGRAM STACK

TIMERS/ POINTER

COUNTERS

OSCILLATOR

COUNTER

PROGRAM

FLASH

SRAM

INTERNAL

OSCILLATOR

XTAL1

INSTRUCTION

REGISTER

GENERAL WATCHDOG

PURPOSE

OSCILLATOR

REGISTERS

TIMER

X

XTAL2

INSTRUCTION

DECODER

Y MCU CTRL.

& TIMING

RESET

Z

CONTROL

INTERNAL

LINES

ALU

INTERRUPT

UNIT

CALIBRATED

OSCILLATOR

AVR CPU

STATUS REGISTER

EEPROM

PROGRAMMING

LOGIC

SPI USART

+ COMP. -

INTERFACE

PORTB DIGITAL INTERFACE

PORTD DIGITAL INTERFACE

PORTB DRIVERS/BUFFERS

PORTD DRIVERS/BUFFERS

PB0 - PB7

PD0 - PD7

8154BS–AVR–07/09

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ATmega16A

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers.

The ATmega16A provides the following features: 16K bytes of In-System Programmable Flash Program memory with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM, 32 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary- scan, On-chip Debugging support and programming, three flexible Timer/Counters with com- pare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscil- lator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next External Inter- rupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/reso- nator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high density nonvolatile memory technology. The On- chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16A is a powerful microcontroller that provides a highly-flexible and cost- effective solution to many embedded control applications.

The ATmega16A AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

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ATmega16A

2.2

Pin Descriptions

2.2.1

VCC

Digital supply voltage.

2.2.2

GND

Ground.

2.2.3

Port A (PA7:PA0)

Port A serves as the analog inputs to the A/D Converter.

Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers have sym-metrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.

2.2.4

Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega16A as listed on page 57.

2.2.5

Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs.

Port C also serves the functions of the JTAG interface and other special features of the ATmega16A as listed on page 60.

2.2.6

Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega16A as listed on page 62.

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ATmega16A

2.2.7

RESET Reset Input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 27-2 on page 296. Shorter pulses are not guaranteed to generate a reset.

2.2.8

XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.2.9

XTAL2

Output from the inverting Oscillator amplifier.

2.2.10

AVCC

AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally con- nected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.

2.2.11

AREF

AREF is the analog reference pin for the A/D Converter.

3. Resources

A comprehensive set of development tools, application notes and datasheets are available for download on

Note:

1.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

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ATmega16A

5. Register Summary

Address Name Bit 7 I–Bit 6 T–Bit 5 H–Bit 4 S–Bit 3 V–Bit 2 NSP10SP2Bit 1 ZSP9SP1Bit 0 CSP8SP0Page $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($23) $02 ($22) $3F ($5F)$3E ($5E)(1) (1)(2) (2) OCR0 GICR GIFR TIMSK TIFR SPMCR TWCR MCUCR MCUCSR TCCR0 TCNT0 OSCCAL OCDR SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 ASSR WDTCR UBRRH UCSRC EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR UCSRA UCSRB UBRRL ACSR ADMUX ADCSRA ADCH ADCL TWDR TWAR SPLSREGSPH Timer/Counter0 Output Compare Register INT1 INT0 INT2 INTF1 INTF0 INTF2 OCIE2 TOIE2 TICIE1 OCF2 TOV2 ICF1 SPMIE RWWSB – TWINT TWEA TWSTA SM2 SE SM1 JTD ISC2 – FOC0 WGM00 COM01 Timer/Counter0 (8 Bits) Oscillator Calibration Register On-Chip Debug Register ADTS2 ADTS1 ADTS0 COM1A1 COM1A0 COM1B1 ICNC1 ICES1 – SP7SP6SP5Timer/Counter1 – Counter Register Low Byte SP4 SP3 OCIE1A OCF1A SM0 – –RWWSRETWSTOJTRF COM00 OCF1B BLBSET TWWC ISC11 WDRF WGM01 OCIE1B – – TOV1 PGWRT TWEN ISC10 BORF CS02 TOIE1 – – 12 85 91269IVSEL– OCF0 PGERS – ISC01 EXTRF CS01 OCIE0 IVCE– TOV0 SPMEN TWIE ISC00 PORF CS00 TOIE0 47, 69– COM1B0Timer/Counter1 – Counter Register High Byte Timer/Counter1 – Output Compare Register B High Byte Timer/Counter1 – Output Compare Register B Low Byte Timer/Counter1 – Input Capture Register High Byte Timer/Counter1 – Input Capture Register Low Byte FOC2 WGM20 COM21 COM20 Timer/Counter2 (8 Bits) Timer/Counter2 Output Compare Register – – – – – – – WDTOE URSEL – – – URSEL UMSEL UPM1 UPM0 – – – – EEPROM Address Register Low Byte EEPROM Data Register – – – – PORTA7 PORTA6 PORTA5 PORTA4 DDA7 DDA6 DDA5 DDA4 PINA7 PINA6 PINA5 PINA4 PORTB7 PORTB6 PORTB5 PORTB4 DDB7 DDB6 DDB5 DDB4 PINB7 PINB6 PINB5 PINB4 PORTC7 PORTC6 PORTC5 PORTC4 DDC7 DDC6 DDC5 DDC4 PINC7 PINC6 PINC5 PINC4 PORTD7 PORTD6 PORTD5 PORTD4 DDD7 DDD6 DDD5 DDD4 PIND7 PIND6 PIND5 PIND4 SPI Data Register SPIF WCOL – – SPIE SPE DORD MSTR USART I/O Data Register RXC TXC UDRE FE RXCIE TXCIE UDRIE RXEN USART Baud Rate Register Low Byte ACD ACBG ACO ACI REFS1 REFS0 ADLAR MUX4 ADEN ADSC ADATE ADIF ADC Data Register High Byte ADC Data Register Low Byte Two-wire Serial Interface Data Register TWA6 TWA5 TWA4 TWA3 Timer/Counter1 – Output Compare Register A High ByteTimer/Counter1 – Output Compare Register A Low Byte WGM13 FOC1A WGM12 ACMEPUD FOC1BCS12 PSR2CS11 WGM11 WGM10 CS10 PSR10 85, 115, 134 255 200 36, 67 41, 68, 249 82 84 31 231 85, 115, 134109112 65,87,134,205,225WGM21 CS22 CS21 CS20 WDE AS2USBS–TCN2UBWDP2 OCR2UBWDP1 UBRR[11:8]UCSZ1– TCR2UBWDP0 UCSZ0– UCPOLEEAR8 EERIEDDA3 PORTA3 PINA3 PINB3 DDB3DDC3 PORTB3PORTC3PINC3DDD3 PORTD3 PIND3 – PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 EEMWE–EEWEDDA1 PORTA1 PINA1 PINB1 DDB1DDC1 EEREDDA0 PORTA0 PINA0 PINB0 DDB0DDC0 PORTB1PORTB0PORTC1PINC1DDD1 PORTC0PINC0DDD0 PORTD1 PIND1 –PORTD0 PIND0 SPI2X CPOLDOR CPHAPE SPR1U2X SPR0 TXB8TXENACIE UCSZ2ACICRXB8 MPCM MUX3 ADIE ADPS2 MUX2 ADPS1 ACIS1MUX1 ADPS0 ACIS0MUX0TWA2 TWA1 TWA0 TWGCE 113 113 114 114 114 114 114 114 130 133 133 133 42 170 169 19 19 20 20 65 65 65 65 65 66 66 66 66 66 66 66 145 144 143 166 167 168 170 205 221 223 224 224 202 203 8

8154BS–AVR–07/09

ATmega16A

Address $01 ($21) $00 ($20) Name TWSR TWBR Two-wire Serial Interface Bit Rate Register TWS7Bit 7 Bit 6 TWS6 Bit 5 TWS5Bit 4 TWS4 Bit 3 TWS3 Bit 2 – Bit 1 TWPS1 Bit 0 TWPS0 Page 202200 Notes: 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debug- ger specific documentation for details on how to use the OCDR Register.

2. Refer to the USART description for details on how to access UBRRH and UCSRC.

3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

4. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.

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ATmega16A

6. Instruction Set Summary

Operands Mnemonics ARITHMETIC AND LOGIC INSTRUCTIONS Rd, Rr ADDADC Rd, Rr ADIW Rdl,K SUB Rd, Rr SUBI Rd, K Rd, Rr SBCSBCI Rd, K SBIW Rdl,K Rd, Rr AND Rd, K ANDI Rd, Rr ORORI Rd, K EOR Rd, Rr Rd COM Rd NEG SBR Rd,K CBR Rd,K INC Rd Rd DEC Rd TST CLR Rd SER Rd MUL Rd, Rr Rd, Rr MULS MULSU Rd, Rr FMUL Rd, Rr FMULS Rd, Rr FMULSU Rd, Rr BRANCH INSTRUCTIONS k RJMPIJMP JMP k RCALL k ICALL CALL k RET RETI Rd,Rr CPSE CP Rd,Rr CPC Rd,Rr CPI Rd,K SBRC Rr, b Rr, b SBRS SBIC P, b SBIS P, b BRBS s, k BRBC s, k k BREQ BRNE k BRCS k BRCC k BRSH k BRLO k k BRMI BRPL k BRGE k BRLT k BRHS k k BRHCBRTS k 8154BS–AVR–07/09

Description Add two RegistersOperation Flags #Clocks Add with Carry two RegistersAdd Immediate to WordSubtract two Registers Rd ? Rd + Rr Rd ? Rd + Rr + CRd ? Rd - Rr Rdh:Rdl ? Rdh:Rdl + KRd ? Rd - KSubtract Constant from RegisterSubtract with Carry two RegistersSubtract Immediate from WordLogical AND RegistersLogical OR Registers Subtract with Carry Constant from Reg. Rd ? Rd - Rr - CRd ? Rd - K - C Rdh:Rdl ? Rdh:Rdl - KLogical AND Register and Constant Logical OR Register and ConstantExclusive OR Registers Two’s Complement One’s Complement Rd ? Rd ? K Rd ? Rd v Rr Rd ? Rd v K Rd ? Rd ? Rr Rd ? Rd ? Rr Set Bit(s) in Register Clear Bit(s) in Register Decrement Increment Rd ? $00 ? Rd Rd ? Rd v K Rd ? $FF ? RdRd ? Rd ? ($FF - K)Rd ? Rd + 1Rd ? Rd ? 1Test for Zero or MinusClear RegisterSet Register Rd ? Rd ? RdRd ? $FF Rd ? Rd ? RdMultiply UnsignedMultiply Signed Multiply Signed with UnsignedFractional Multiply UnsignedFractional Multiply Signed R1:R0 ? Rd x Rr R1:R0 ? Rd x Rr R1:R0 ? Rd x Rr Fractional Multiply Signed with UnsignedRelative JumpDirect Jump R1:R0 ? (Rd x Rr) << 1 R1:R0 ? (Rd x Rr) << 1 R1:R0 ? (Rd x Rr) << 1PC ? PC + k + 1 Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C Z,C,N,V,HZ,C,N,V,H 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 11 Indirect Jump to (Z) PC ? k PC ? ZPC ? ZPC ? k Relative Subroutine CallIndirect Call to (Z)Subroutine ReturnInterrupt ReturnCompare PC ? PC + k + 1Direct Subroutine Call PC ? STACKPC ? STACKRd ? RrRd ? K Compare, Skip if Equal if (Rd = Rr) PC ? PC + 2 or 3Compare with Carry None None None None None None I None NoneRd ? Rr ? CCompare Register with ImmediateSkip if Bit in Register ClearedSkip if Bit in Register is SetSkip if Bit in I/O Register ClearedSkip if Bit in I/O Register is SetBranch if Status Flag SetBranch if Equal if (Rr(b)=1) PC ? PC + 2 or 3 if (P(b)=0) PC ? PC + 2 or 3 if (P(b)=1) PC ? PC + 2 or 3 if (Rr(b)=0) PC ? PC + 2 or 3 Branch if Status Flag Cleared Branch if Carry Set Branch if Not Equal Branch if Carry Cleared Branch if Same or Higher Branch if Minus Branch if Plus Branch if Lower Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if Greater or Equal, Signed if (SREG(s) = 0) then PC?PC+k + 1 if (Z = 1) then PC ? PC + k + 1 if (Z = 0) then PC ? PC + k + 1 if (C = 1) then PC ? PC + k + 1 if (C = 0) then PC ? PC + k + 1 if (C = 0) then PC ? PC + k + 1 if (C = 1) then PC ? PC + k + 1 if (N = 1) then PC ? PC + k + 1 if (N = 0) then PC ? PC + k + 1 if (N ? V= 0) then PC ? PC + k + 1 if (N ? V= 1) then PC ? PC + k + 1 if (H = 1) then PC ? PC + k + 1 if (H = 0) then PC ? PC + k + 1 if (T = 1) then PC ? PC + k + 1 if (SREG(s) = 1) then PC?PC+k + 1 Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None Z, N,V,C,H 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 210

ATmega16A

Mnemonics Operands Description Branch if T Flag ClearedOperation BRVC BRIE BRID BRTCBRVSMOV k k k kk Branch if Overflow Flag is Set Branch if Overflow Flag is ClearedDATA TRANSFER INSTRUCTIONS MOVW LD LD LD LD LD LD LDI LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT LDDPOPSBI LD LDLD Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Rd, RrRd, RrRd, Z Branch if Interrupt Disabled Branch if Interrupt EnabledMove Between RegistersCopy Register WordLoad ImmediateLoad Indirect if (V = 0) then PC ? PC + k + 1 if ( I = 1) then PC ? PC + k + 1 if ( I = 0) then PC ? PC + k + 1 if (T = 0) then PC ? PC + k + 1if (V = 1) then PC ? PC + k + 1Rd ? RrRd+1:Rd ? Rr+1:Rr Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect and Post-Inc.Load Indirect Load Indirect with Displacement Load Indirect and Pre-Dec. Load Indirect and Post-Inc.Load Direct from SRAMStore Indirect Load Indirect with Displacement Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect and Post-Inc.Store Indirect Store Indirect with Displacement Store Indirect and Pre-Dec. Store Indirect and Post-Inc.Store Direct to SRAM Store Indirect with Displacement Rd, Z+Rd, PP, RrRrRd Load Program Memory Load Program MemoryStore Program MemoryIn Port Load Program Memory and Post-IncPUSH Out Port Push Register on Stack Pop Register from StackSet Bit in I/O RegisterLogical Shift Left X ? X - 1, Rd ? (X) Rd ? (Y) Rd ? (Y), Y ? Y + 1 Y ? Y - 1, Rd ? (Y) Rd ? (Y + q) Rd ? (Z) Rd ? (Z), Z ? Z+1 Z ? Z - 1, Rd ? (Z) Rd ? (Z + q) Rd ? (k) (X) ? Rr (X) ? Rr, X ? X + 1 X ? X - 1, (X) ? Rr (Y) ? Rr (Y) ? Rr, Y ? Y + 1 Y ? Y - 1, (Y) ? Rr (Y + q) ? Rr (Z) ? Rr (Z) ? Rr, Z ? Z + 1 Z ? Z - 1, (Z) ? Rr (Z + q) ? Rr (k) ? Rr R0 ? (Z) Rd ? (Z) Rd ? (Z), Z ? Z+1 (Z) ? R1:R0 Rd ? P P ? Rr STACK ? Rr Rd ? STACK Rd ? (X), X ? X + 1 Rd ? (X) Rd ? K BIT AND BIT-TEST INSTRUCTIONS CBI LSL LSR ROL ROR ASR BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SWAP P,b Rd Rd Rd Rd Rd Rd s s P,b Clear Bit in I/O Register I/O(P,b) ? 0 I/O(P,b) ? 1Logical Shift Right Rd(n+1) ? Rd(n), Rd(0) ? 0Rd(n) ? Rd(n+1), Rd(7) ? 0 Rotate Left Through CarryArithmetic Shift RightSwap NibblesFlag SetRotate Right Through Carry Rd(0)?C,Rd(n+1)? Rd(n),C?Rd(7)Rd(7)?C,Rd(n)? Rd(n+1),C?Rd(0)Rd(n) ? Rd(n+1), n=0:6 Rd, b Rr, bFlag Clear Bit Store from Register to TBit load from T to RegisterSet Carry Clear Carry Set Negative FlagSet Zero Flag Clear Negative FlagClear Zero Flag Global Interrupt EnableSet Signed Test FlagGlobal Interrupt DisableClear Signed Test Flag Set Twos Complement Overflow.Clear Twos Complement Overflow SREG(s) ? 0 T ? Rr(b) Rd(b) ? T C ? 1 C ? 0 N ? 1 N ? 0 Z ? 1 Z ? 0 I ? 1 I ? 0 S ? 1 S ? 0 V ? 1 V ? 0 SREG(s) ? 1Rd(3:0)?Rd(7:4),Rd(7:4)?Rd(3:0) 8154BS–AVR–07/09

Flags None None None None None None None None None None None None None None None None None None NoneNone None None None NoneNone None None None None None None None None None None None None None None None None NoneZ,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,VNone SREG(s) SREG(s) T NoneC C N N Z Z I I S S V V

#Clocks 1/2 1/2 1/2 1/21/2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 - 1 1 2 2 11 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 211

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