SelectMAP Configuration Interface
BitGen. By default, the SelectMAPx8 interface (D0–D7) is preserved unless another SelectMAP width has been selected with the CONFIG_MODE constraint.
Reconfiguration begins when the synchronization word is clocked into the SelectMAP port. The remainder of the operation is identical to configuration as described above.
SelectMAP Data Ordering
In many cases, SelectMAP configuration is driven by a user application residing on a microprocessor, CPLD, or in some cases another FPGA. In these applications, it is
important to understand how the data ordering in the configuration data file corresponds to the data ordering expected by the FPGA.
In SelectMAP x8 mode, configuration data is loaded at one byte per CCLK, with the MSB of each byte presented to the D0 pin. This convention (D0 = MSB, D7 = LSB) differs from many other devices. For x16 and x32 modes, see “Parallel Bus Bit Order.” This convention can be a source of confusion when designing custom configuration solutions. Table2-6 shows how to load the hexadecimal value 0xABCD into the SelectMAP data bus. Table 2-6:Bit Ordering for SelectMAP 8-Bit ModeCCLK Cycle
12
Notes:
1.D[0:7] represent the SelectMAP DATA pins.
Hex Equivalent
0xAB0xCD
D011
D101
D210
D300
D411
D501
D610
D711
Some applications can accommodate the non-conventional data ordering without
difficulty. For other applications, it can be more convenient for the source configuration data file to be bit swapped, meaning that the bits in each byte of the data stream are reversed. For these applications, the Xilinx PROM file generation software can generate bit-swapped PROM files (see “Configuration Data File Formats”).
Figure2-19 shows the bit ordering for x8, x16, and x32 modes. It also shows the bit ordering for Virtex-4 FPGA x32 mode.
Virtex-5 Modex32x16x8
Pin
3130292827262524232221202418171615141312111024252627282930311617181920242223
88
99
9
8
7000
6111
5222
4333
3444
2555
1666
0777
101112131415101112131415
Virtex-4x32 Mode
31302928272625242322212024181716151413121110
9
8
7
6
5
4
3
2
1
0
Figure 2-19:Bit Ordering
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
Board Layout for Configuration Clock (CCLK)
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
Chapter 2:Configuration Interfaces
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
Chapter 3:Boundary-Scan and JTAG Configuration
Capture-DR:
In this controller state, the data is parallel-loaded into the data registers selected by the current instruction on the rising edge of TCK.
Shift-Dr, Exit1-DR, Pause-DR, Exit2-DR, and Update-DR:
These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR, and Update-IR states in the Instruction path.
10TEST-LOGIC-RESET0RUN-TEST/IDLE1SELECT-DR-SCAN10CAPTURE-DR0SHIFT-DR1EXIT1-DR0PAUSE-DR01EXIT2-DR1UPDATE-DR10100101SELECT-IR-SCAN10CAPTURE-IR0SHIFT-IR1EXIT1-IR0PAUSE-IR1EXIT2-IR1UPDATE-IR00101NOTE: The value shown adjacent to each state transition in this figurerepresents the signal present at TMS at the time of a rising edge at TCK.
UG191_c3_02_050406
Figure 3-2:Boundary-Scan TAP Controller
Virtex-5 devices support the mandatory IEEE 1149.1 commands, as well as several Xilinx vendor-specific commands. The EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,
IDCODE, USERCODE, and HIGHZ instructions are all included. The TAP also supports internal user-defined registers (USER1, USER2, USER3, and USER4) and configuration/readback of the device.
The Virtex-5 Boundary-Scan operations are independent of mode selection. The
Boundary-Scan mode in Virtex-5 devices overrides other mode selections. For this reason, Boundary-Scan instructions using the Boundary-Scan register (SAMPLE/PRELOAD, INTEST, and EXTEST) must not be performed during configuration. All instructions except the user-defined instructions are available before a Virtex-5 device is configured. After configuration, all instructions are available.
JSTART and JSHUTDOWN are instructions specific to the Virtex-5 architecture and
configuration flow. In Virtex-5 devices, the TAP controller is not reset by the PROGRAM_B pin and can only be reset by bringing the controller to the TLR state. The TAP controller is reset on power up.
For details on the standard Boundary-Scan instructions EXTEST, INTEST, and BYPASS, refer to the IEEE Standard.
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1
Boundary-Scan Architecture
Virtex-5 device registers include all registers required by the IEEE 1149.1 Standard. In addition to the standard registers, the family contains optional registers for simplified testing and verification (Table3-2).
Table 3-2:Virtex-5 Device JTAG Registers
Register NameBoundary-Scan RegisterInstruction RegisterBYPASS RegisterIdentification RegisterJTAG Configuration RegisterUSERCODE RegisterUser-Defined Registers (USER1, USER2, USER3, andUSER4)
Register Length3 bits per I/O10 or 14 bits
1 bit32 bits32 bits32 bitsDesign-specific
Description
Controls and observes input, output, and output enable
Holds current instruction OPCODE and captures internal device statusBypasses the deviceCaptures the Device ID
Allows access to the configuration bus when using the CFG_IN or CFG_OUT instructions
Captures the user-programmable codeDesign-specific
Boundary-Scan Register
The test primary data register is the Boundary-Scan register. Boundary-Scan operation is independent of individual IOB configurations. Each IOB, bonded or unbonded, starts as bidirectional with 3-state control. Later, it can be configured to be an input, output, or 3-state only. Therefore, three data register bits are provided per IOB (Figure3-3).
When conducting a data register (DR) operation, the DR captures data in a parallel fashion during the CAPTURE-DR state. The data is then shifted out and replaced by new data during the SHIFT-DR state. For each bit of the DR, an update latch is used to hold the input data stable during the next SHIFT-DR state. The data is then latched during the UPDATE-DR state when TCK is Low.
The update latch is opened each time the TAP controller enters the UPDATE-DR state. Care is necessary when exercising an INTEST or EXTEST to ensure that the proper data has been latched before exercising the command. This is typically accomplished by using the SAMPLE/PRELOAD instruction.
Internal pull-up and pull-down resistors should be considered when test vectors are being developed for testing opens and shorts. The HSWAPEN pin determines whether the IOB has a pull-up resistor. Figure3-3 is a representation of Virtex-5 Boundary-Scan architecture.
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
FPGA可编程逻辑器件芯片XC2S200-5FG456C中文规格书 - 图文
