NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
8.9.1Features
?Eight DMA channels. Each channel can support an unidirectional transfer.?16 DMA request lines.
?Single DMA and burst DMA request signals. Each peripheral connected to the DMA
Controller can assert either a burst DMA request or a single DMA request. The DMAburst size is set by programming the DMA Controller.
?Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers are supported.
?Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
?Hardware DMA channel priority.
?AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
?One AHB bus master for transferring data. The interface transfers data when a DMA
request goes active.
?32-bit AHB master bus width.
?Incrementing or non-incrementing addressing for source and destination.
?Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
?Internal four-word FIFO per channel.
?Supports 8, 16, and 32-bit wide transactions.
?Big-endian and little-endian support. The DMA Controller defaults to little-endian
mode on reset.
?An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
?Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
8.10Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins.LPC17xx use accelerated GPIO functions:
?GPIO registers are accessed through the AHB multilayer bus so that the fastest
possible I/O timing can be achieved.
?Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
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LPC1769_68_67_66_65_64_63
All GPIO registers are byte and half-word addressable.Entire port value can be written in one instruction.Support for Cortex-M3 bit banding.Support for use with the GPDMA controller.
All information provided in this document is subject to legal disclaimers.
? NXP Semiconductors N.V. 2020. All rights reserved.
Product data sheetRev. 9.10 — 8 September 2020 25 of 93
NXP Semiconductors
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode.
8.10.1Features
?Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
?Direction control of individual bits.?All I/O default to inputs after reset.
?Pull-up/pull-down resistor configuration and open-drain configuration can be
programmed through the pin connect block for each GPIO pin.
8.11Ethernet
Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The Ethernet block supports bus clock rates of up to 100 MHz (LPC1768/67/66/64) or 120 MHz (LPC1769). See Table 2.
The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware
acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share the Arm Cortex-M3 D-code and system bus through the AHB-multilayer matrix to access the various on-chip SRAM blocks for Ethernet data, control, and status information.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus.
8.11.1Features
?Ethernet standards support:
–Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,100 Base-FX, and 100 Base-T4.–Fully compliant with IEEE standard 802.3.
–Fully compliant with 802.3x full duplex flow control and half duplex back pressure.–Flexible transmit and receive frame options.–Virtual Local Area Network (VLAN) frame support.
?Memory management:
–Independent transmit and receive buffers memory mapped to shared SRAM.–DMA managers with scatter/gather DMA and arrays of frame descriptors.–Memory traffic optimized by buffering and pre-fetching.
LPC1769_68_67_66_65_64_63
All information provided in this document is subject to legal disclaimers.
? NXP Semiconductors N.V. 2020. All rights reserved.
Product data sheet
Rev. 9.10 — 8 September 2020 26 of 93
MEMORY存储芯片MPC8265ACZUMHBC中文规格书 - 图文
