AD7708/AD7718
I/O Control Register (IOCON): (A3, A2, A1, A0 = 0, 1, 1, 1; Power-On-Reset = 00Hex)The IOCON Register is an 8-bit register from which data can be read or to which data can be written. This register is used to con-trol and configure the I/O port. Table XIX outlines the bit designations for this register. IOCON7 through IOCON0 indicate thebit location, IOCON denoting the bits are in the I/O Control Register. IOCON7 denotes the first bit of the data stream. The num-ber in brackets indicates the power-on/reset default status of that bit. A write to the IOCON register has immediate effect and doesnot reset the ADCs.IOCON7(0)IOCON60(0)IOCON5P2DIR(0)IOCON4P1DIR(0)IOCON30(0)IOCON20(0)IOCON1P2DAT(0)IOCON0P1DAT(0)Table XIX.IOCON (I/O Control Register) Bit DesignationsBitLocationIOCON7IOCON6IOCON5BitMnemonic00P2DIRDescriptionThis bit should always be cleared. Reserved for future use.This bit should always be cleared. Reserved for future use.P2, I/O Direction Control Bit.Set by user to enable P2 as an output.Cleared by user to enable P2 as an input. There are weak pull-ups internally when enabledas an input.P1, I/O Direction Control Bit.Set by user to enable P1 as an output.Cleared by user to enable P1 as an input. There are weak pull-ups internally when enabledas an input.This bit should always be cleared. Reserved for future use.This bit should always be cleared. Reserved for future use.Digital I/O Port (P1) Data Bit.The readback value of this bit indicates the status of the pin regardless of whether this pin isconfigured as an input or an output. The value written to this data bit will appear at theoutput port when the I/O pin is enabled as an output.Digital I/O port (P1) Data Bit.The readback value of this bit indicates the status of the pin, regardless of whether this pin isconfigured as an input or an output. The value written to this data bit will appear at theoutput port when the I/O pin is enabled as an output.IOCON4P1DIRIOCON3IOCON2IOCON100P2DATIOCON0P1DATADC Data Result Register (DATA): (A3, A2, A1, A0 = 0, 1, 0, 0; Power-On-Reset = 000000Hex)The conversion result for the selected ADC channel is stored in the ADC data register (DATA). This register is 16 bits wide on theAD7708 and 24 bits wide on the AD7718. This is a read only register. On completion of a read from this register the RDY bit inthe status register is cleared. These ADCs can be operated in either unipolar or bipolar mode of operation.Unipolar ModeIn unipolar mode of operation the output coding is straight binary. With an analog input voltage of 0 V the output code is 0000Hexfor the AD7708 and 000000Hex for the AD7718. With an analog input voltage of 1.024 VREF/Gain the output code is FFFFHexfor the AD7708 and FFFFFF Hex for the AD7718. The output code for any analog input voltage can be represented as follows:Code = (AIN × GAIN × 2N)/(1.024 × VREF)whereAIN is the analog input voltage andN = 16 for the AD7708 and N = 24 for the AD7718.–30–REV. 0
AD7708/AD7718
Bipolar ModeWith an analog input voltage of (–1.024 VREF/GAIN), the output code is 0000 Hex using the AD7708 and 000000H using the AD7718.With an analog input voltage of 0 V, the output code is 8000Hex for the AD7708 and 800000Hex for the AD7718. With an analoginput voltage of (+1.024 VREF/GAIN), the output code is FFFF Hex for the AD7708 and FFFFFF Hex for the AD7718. Note theanalog inputs are pseudo bipolar inputs and the analog input voltage must remain within the common-mode input range at all times.The output code for any analog input voltage can be represented as follows:Code = 2N–1 × [(AIN × GAIN/1.024 × VREF) + 1]whereAIN is the analog input voltage,N = 16 for the AD7708, andN = 24 for the AD7718.ADC Offset Calibration Coefficient Registers (OF0): (A3, A2, A1, A0 = 0, 1, 0, 1; Power-On-Reset = 8000(00)Hex)The offset calibration registers are 16-bit registers on the AD7708 and 24-bit registers on the AD7718. These registers hold the offsetcalibration coefficient for the ADC. The power-on-reset value of the internal zero-scale calibration coefficient registers is 8000(00).There are five offset registers available, one for each of the fully differential input channels. Calibration register pairs are shared whenoperating in pseudo-differential input mode. However, these bytes will be automatically overwritten if an internal or system zero-scalecalibration is initiated by the user via MD2–MD0 bits in the MODE register. The channel bits, in association with the communicationregister address for the OF0 register, allow access to this register. This register is a read/write register. The calibration register canonly be written to if the ADC is inactive (MD bits in the mode register = 000 or 001). Reading of the calibration register does notclear the RDY bit.ADC Gain Calibration Coefficient Register (GNO): (A3, A2, A1, A0 = 0, 1, 1, 0; Power-On-Reset = 5XXX(X5) Hex)The gain calibration registers are 16-bit registers on the AD7708 and 24-bit registers on the AD7718. These registers are configuredat power-on with factory-calculated internal full-scale calibration coefficients. There are five full-scale registers available, one for eachof the fully differential input channels. Calibration register pairs are shared when operating in pseudo-differential input mode. Everydevice will have different default coefficients. However, these bytes will be automatically overwritten if an internal or system full-scalecalibration is initiated by the user via MD2–MD0 bits in the MODE register. The channel bits, in association with the communicationregister address, allow access to the data contained in the GN0 register. This is a read/write register. The calibration registers canonly be written to if the ADC is inactive (MD bits in the mode register = 000 or 001). Reading of the calibration registers does notclear the RDY bit. A calibration (self or system) is required when operating with chop mode disabled.ID Register (ID): (A3, A2, A1, A0 = 1, 1, 1, 1; Power-On-Reset = 4X Hex (AD7718) and 5X Hex (AD7708)This register is a read only 8-bit register. The contents are used to determine the die revision of the silicon. Table XX indicates thebit locations for the AD7708.Table XX.ID Register Bit DesignationID70ID61ID50ID40/1ID3XID2XID1XID0XUser Nonprogrammable Test RegistersThe AD7708 and AD7718 contain two test registers. The bits in these test registers control the test modes of these ADCs which areused for the testing of the device. The user is advised not to change the contents of these registers.REV. 0–31–
半导体传感器AD7718BRZ中文规格书 - 图文
