FPGA可编程逻辑器件芯片EP1S20F780C6中文规格书 - 图文

Figure1–15 shows the timing waveform for the lock and gated lock signals.

Figure1–15.Timing Waveform for Lock and Gated Lock Signals

PLL_ENAReference ClockFeedback ClockLockFilter CounterReachesValue CountGated LockThe device resets and enables both the counter and the PLL

simultaneously when the pllena signal is asserted or the areset signal is de-asserted. Enhanced PLLs and fast PLLs support this feature. To ensure correct circuit operation, and to ensure that the output clocks have the correct phase relationship with respect to the input clock, Altera recommends that the input clock be running before the StratixII device is finished configuring.

PLL_ENA

The PLL_ENA pin is a dedicated pin that enables or disables all PLLs on the StratixII or Stratix II GX device. When the PLL_ENA pin is low, the clock output ports are driven low and all the PLLs go out of lock. When the PLL_ENA pin goes high again, the PLLs relock and resynchronize to the input clocks. You can choose which PLLs are controlled by the pllena signal by connecting the pllena input port of the altpll megafunction to the common PLL_ENA input pin.

Also, whenever the PLL loses lock for any reason (be it excessive inclk jitter, clock switchover, PLL reconfiguration, power supply noise, etc.), the PLL must be reset with the areset signal to guarantee correct phase relationship between the PLL output clocks. If the phase relationship between the input clock versus output clock, and between different

output clocks from the PLL is not important in your design, the PLL need not be reset.

Stratix II Device Handbook, Volume 2

PLLs in StratixII and StratixIIGX Devices

Figure1–24.Manual Switchover

inclk0Note(1)

inclk1muxoutclkswitchNote to Figure1–24:(1)

Both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate a manual clockswitchover event. Failing to meet this requirement causes the clock switchover to not function properly.

Software Support

Table1–15 summarizes the signals used for clock switchover.

Table1–15.altpll Megafunction Clock Switchover Signals

Port

inclk0inclk1clkbad0(1)clkbad1(1)clkswitch

(Part 1 of2)

Source

I/O pinI/O pin

Description

Reference clk0 to the PLL.Reference clk1 to the PLL.

Destination

Clock switchover circuitClock switchover circuitLogic arrayLogic array

Clock switchover circuit

Signal indicating that inclk0 is no longer Clock switchover toggling.circuitSignal indicating that inclk1 is no longer Clock switchover toggling.circuitLogic array or I/O pinSwitchover signal used to initiate clock switchover asynchronously. When used in manual switchover, clkswitch is used as a select signal between inclk0 and inclk1 clswitch = 0 inclk0 is selected and vice versa.

Signal indicating that the switchover circuit detected a switch condition.Signal indicating that the PLL has lost lock.

Clock switchover circuitPLL

clkloss(1)locked

Logic array

Clock switchover circuit

Stratix II Device Handbook, Volume 2

Advanced Features

Stratix II Device Handbook, Volume 2

PLLs in StratixII and StratixIIGX Devices

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Applications that require a clock switchover feature and a smallfrequency drift should use a low-bandwidth PLL. The

low-bandwidth PLL reacts slower than a high-bandwidth PLL toreference input clock changes. When the switchover happens, alow-bandwidth PLL propagates the stopping of the clock to theoutput slower than a high-bandwidth PLL. A low-bandwidth PLLfilters out jitter on the reference clock. However, be aware that thelow-bandwidth PLL also increases lock time.

StratixII and Stratix II GX device PLLs can use both the automaticclock switchover and the clkswitch input simultaneously.

Therefore, the switchover circuitry can automatically switch from the primary to the secondary clock. Once the primary clock stabilizesagain, the clkswitch signal can switch back to the primary clock.During switchover, the PLL_VCO continues to run and slows down,generating frequency drift on the PLL outputs. The clkswitchsignal controls switchover with its rising edge only.

If the clock switchover event is glitch-free, after the switch occurs,there is still a finite resynchronization period to lock onto a new clock as the VCO ramps up. The exact amount of time it takes for the PLLto relock is dependent on the PLL configuration. Use the PLLprogrammable bandwidth feature to adjust the relock time.

If the phase relationship between the input clock to the PLL andoutput clock from the PLL is important in your design, assertareset for 10ns after performing a clock switchover. Wait for thelocked signal (or gated lock) to go high before re-enabling the outputclocks from the PLL.

Figure1–25 shows how the VCO frequency gradually decreaseswhen the primary clock is lost and then increases as the VCO lockson to the secondary clock. After the VCO locks on to the secondaryclock, some overshoot can occur (an over-frequency condition) in the VCO frequency.

Figure1–25.VCO Switchover Operating Frequency

Primary Clock Stops RunningFrequency OvershootSwitchover Occurs VCO Tracks Secondary Clock vcoΔFStratix II Device Handbook, Volume 2

PLLs in StratixII and StratixIIGX Devices

Figure1–28.High-Bandwidth PLL Lock Time

160155Lock Time = 4 μs150145Frequency (MHz)14013513012512000.51.01.52.02.5Time (μs)3.03.54.04.55.0A high-bandwidth PLL can benefit a system that has two cascaded PLLs. If the first PLL uses spread spectrum (as user-induced jitter), the second PLL can track the jitter that is feeding it by using a high-bandwidth setting. A low-bandwidth PLL can, in this case, lose lock due to the spread-spectrum-induced jitter on the input clock.

A low-bandwidth PLL benefits a system using clock switchover. When the clock switchover happens, the PLL input temporarily stops. A low-bandwidth PLL would react more slowly to changes to its input clock and take longer to drift to a lower frequency (caused by the input stopping) than a high-bandwidth PLL. Figures1–29 and 1–30 demonstrate this property. The two plots show the effects of clock switchover with a low- or high-bandwidth PLL. When the clock switchover happens, the output of the low-bandwidth PLL (see Figure1–29) drifts to a lower frequency more slowly than the high-bandwidth PLL output (see Figure1–30).

Stratix II Device Handbook, Volume 2