C16 column interconnects span a length of 16 LABs and provide the fastest resource for long column connections between LABs, TriMatrix memory blocks, DSP blocks, and IOEs. C16 interconnects can cross
M-RAM blocks and also drive to row and column interconnects at everyfourth LAB. C16 interconnects drive LAB local interconnects via C4 andR4 interconnects and do not drive LAB local interconnects directly.All embedded blocks communicate with the logic array similar to LAB-to-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks, labclk[5..0].Table2–2 shows the StratixII device’s routing scheme.
Table2–2. StratixII Device Routing Scheme(Part 1 of2)
Destination
Shared Arithmetic ChainDirect Link InterconnectLocal InterconnectM512 RAM BlockR24 InterconnectC16 InterconnectM4K RAM BlockR4 InterconnectC4 InterconnectRegister ChainM-RAM BlockCarry ChainColumn IOEDSP BlocksShared arithmetic chainCarry chainRegister chainLocal interconnectDirect link interconnectR4 interconnectR24 interconnectC4 interconnectC16 interconnectALM
M512 RAM blockM4K RAM blockM-RAM blockDSP blocks
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Stratix II Device Handbook, Volume 1
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ALMSource
Row IOETriMatrix Memory
Table2–2. StratixII Device Routing Scheme(Part 2 of2)
Destination
Shared Arithmetic ChainDirect Link InterconnectLocal InterconnectM512 RAM BlockR24 InterconnectC16 InterconnectM4K RAM BlockR4 InterconnectC4 InterconnectRegister ChainM-RAM BlockCarry ChainColumn IOEDSP BlocksColumn IOERow IOE
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TriMatrix Memory
TriMatrix memory consists of three types of RAM blocks: M512, M4K, and M-RAM. Although these memory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. Table2–3 shows the size and features of the different RAM blocks.
Table2–3.TriMatrix Memory Features(Part 1 of2)
Memory Feature
Maximum performance True dual-port memorySimple dual-port memorySingle-port memoryShift registerROMFIFO bufferPack modeByte enable
Address clock enableParity bitsMixed clock modeMemory initialization (.mif)
M512 RAM Block (32×18 Bits)
500 MHz
M4K RAM Block (128×36 Bits)
550 MHz
ALMSource
M-RAM Block(4K×144Bits)
420 MHz
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(1)
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Stratix II Device Handbook, Volume 1
Row IOEStratixII Architecture
Table2–3.TriMatrix Memory Features(Part 2 of2)
Memory Feature
Simple dual-port memory mixed width supportTrue dual-port memory mixed width supportPower-up conditionsRegister clearsConfigurations
Outputs clearedOutput registers512 × 1256 × 2128 × 464 × 864 × 932 × 1632 × 18
M512 RAM Block (32×18 Bits)
v
M4K RAM Block (128×36 Bits)
vv
Outputs clearedOutput registers4K × 12K × 21K × 4512 × 8512 × 9256 × 16256 × 18128 × 32128 × 36
M-RAM Block(4K×144Bits)
vv
Outputs unknownOutput registers64K × 864K × 932K × 1632K × 1816K × 3216K × 368K × 648K × 724K × 1284K × 144
Mixed-port read-during-writeUnknown output/old dataUnknown output/old dataUnknown output
Notes to Table2–3:(1)
The M-RAM block does not support memory initialization. However, the M-RAM block can emulate a ROM function using a dual-port RAM bock. The StratixII device must write to the dual-port memory once and then disable the write-enable ports afterwards.
Memory Block Size
TriMatrix memory provides three different memory sizes for efficient application support. The QuartusII software automatically partitions the user-defined memory into the embedded memory blocks using the most efficient size combinations. You can also manually assign the memory to a specific block size or a mixture of block sizes.
When applied to input registers, the asynchronous clear signal for the TriMatrix embedded memory immediately clears the input registers. However, the output of the memory block does not show the effects until the next clock edge. When applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately.
Stratix II Device Handbook, Volume 1
TriMatrix Memory
Stratix II Device Handbook, Volume 1
StratixII Architecture
Stratix II Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP1S40F1020C5中文规格书 - 图文
