1 TMS320C6678 Features and Description
1.1Features
?Eight TMS320C66x? DSP Core Subsystems (C66xCorePacs), Each with
–1.0 GHz, 1.25 GHz, or 1.4 GHz C66xFixed/Floating-Point CPU Core
?44.8 GMAC/Core for Fixed Point @ 1.4 GHz?22.4 GFLOP/Core for Floating Point @ 1.4 GHz–Memory
?32K Byte L1P Per Core?32K Byte L1D Per Core
?512K Byte Local L2 Per Core?Multicore Shared Memory Controller (MSMC)
–4096KB MSM SRAM Memory Shared by Eight DSPC66x CorePacs
–Memory Protection Unit for Both MSM SRAM andDDR3_EMIF?Multicore Navigator
–8192 Multipurpose Hardware Queues with QueueManager
–Packet-Based DMA for Zero-Overhead Transfers?Network Coprocessor
–Packet Accelerator Enables Support for
?Transport Plane IPsec, GTP-U, SCTP, PDCP?L2 User Plane PDCP (RoHC, Air Ciphering)
?1-Gbps Wire-Speed Throughput at 1.5 MPacketsPer Second
–Security Accelerator Engine Enables Support for?IPSec, SRTP, 3GPP, WiMAX Air Interface, andSSL/TLS Security
?ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC,GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1,SHA-2 (256-bit Hash), MD5
?Up to 2.8 Gbps Encryption Speed
?Peripherals
–Four Lanes of SRIO 2.1
?1.24/2.5/3.125/5 GBaud Operation Supported PerLane
?Supports Direct I/O, Message Passing
?Supports Four 1×, Two 2×, One 4×, and Two 1× +One 2× Link Configurations–PCIe Gen2
?Single Port Supporting 1 or 2 Lanes?Supports Up To 5GBaud Per Lane–HyperLink
?Supports Connections to Other KeyStoneArchitecture Devices Providing ResourceScalability
?Supports up to 50 Gbaud
–Gigabit Ethernet (GbE) Switch Subsystem?Two SGMII Ports
?Supports 10/100/1000 Mbps Operation–64-Bit DDR3 Interface (DDR3-1600)?8G Byte Addressable Memory Space–16-Bit EMIF
–Two Telecom Serial Ports (TSIP)?Supports 1024 DS0s Per TSIP
?Supports 2/4/8 Lanes at 32.768/16.384/8.192 Mbps Per Lane–UART Interface2
–IC Interface–16 GPIO Pins–SPI Interface
–Semaphore Module–Sixteen 64-Bit Timers–Three On-Chip PLLs?Commercial Temperature:–0°C to 85°C?Extended Temperature:
to 100°C–-40°C
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and
other important disclaimers. PRODUCTION DATA.
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691E—March 2014
For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating point capability and the per-core raw computational performance in an industry-leading 44.8GMACS/core and 22.4GFLOPS/core (@1.4GHz operating frequency). It can execute 8 single-precision floating point MAC operations per cycle and can perform double- and mixed-precision operations, and is IEEE754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating point and vector math oriented processing. These enhancements yield sizeable performance
improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backwards code-compatible with TI's previous generation C6000 fixed and floating point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.
The C6678 DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, there is 512KB of dedicated memory per core that can be configured as mapped RAM or cache. The device also integrates 4096KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 external memory interface (EMIF) running at 1600 MHz and has ECC DRAM support.This family supports a plethora of high speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and
2
Gigabit Ethernet, as well as an integrated Ethernet switch. It also includes IC, UART, Telecom Serial Interface Port (TSIP), and a 16-bit EMIF, along with general purpose CMOS IO. For high throughput, low latency communication between devices or with an FPGA, this device also sports a 50-Gbaud full-duplex interface called HyperLink. Adding to the network awareness of this device is a network co-processor that includes both packet and optional security acceleration. The packet accelerator can process up to 1.5 M packets/s and enables a single IP address to be used for the entire multicore C6678 device. It also provides L2 to L4 classification, along with checksum and QoS capabilities. The C6678 device has a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows? debugger interface for visibility into source code execution.
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TMS320C6678 Features and Description3
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