Chapter 5:Configuration Details
Reserving Dual-Purpose Configuration Pins (Persist)
Dual-purpose pins serve as configuration pins and user I/Os after configuration. The BitGen option -g Persist is used to reserve these pins as configuration pins (see Table5-3 for the settings).
Table 5-3:Dual-Purpose Configuration Pin Settings
Pin Name
DIN/D0/MISO/MISO[1]
D1/MISO2D2/MISO3D[15:3]DOUTINIT_B(2)RDWR_BM0M1HSWAPENCCLK
GCLK0/USERCCLK
CSO_B
MOSI/MISO0/CSI_B
AWAKE(3)A[25:0](4)SCP[7:0](3)FCS_BFOE_BFWE_BHDCLDC
Notes:
1.2.3.4.
All 16 data pins are persisted regardless of whether the SelectMAP data width is x8 or x16.
INIT_B is persisted if readback CRC is enabled, regardless of the POST_CRC_INIT_FLAG setting.AWAKE and SCP[7:0] are activated based on the suspend setting.
A24 and A25 are in bank 5 in larger devices with 6 or more I/O banks.
Bank2222122220222211011111
SelectMAPPersistPersistPersistPersist(1)PersistPersist(2)PersistNoNoNoPersistNoNoPersistNoNoNoNoNoNoNoNo
BPINoNoNoNoNoNo(2)NoNoNoNoNoNoNoNoNoNoNoNoNoNoNoNo
SPI/SerialPersistNoNoNoPersistPersist(2)
NoNoNoNoPersistNoNoNoNoNoNoNoNoNoNoNo
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Configuration Packets
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 6:Readback and Configuration Verification
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Chapter 5:Configuration Details
Configuration Options Register (COR1 and COR2)
The Configuration Options Register is used to set certain configuration options for the device. The name of each bit position in COR1 and COR2 is given in Table5-36.
Table 5-36:RegisterCOR1
Configuration Options (COR1 and COR2) Descriptions
FieldDRIVE_AWAKERESERVEDCRC_BYPASSDONE_PIPEDRIVE_DONESSCLKSRC
Bit Index
1514:54321:0
Description
0: Does not drive the awake pin (open drain).1: Actively drives the awake pin.Reserved.
Does not check against the updated CRC value.0: No pipeline stage for DONEIN.1: Add pipeline stage to DONEIN.0: DONE pin is open drain.
1: DONE pin is actively driven High.Startup sequence clock.00: CCLK.01: UserClk.1x: TCK.
Option to fallback when a crc_error occurs.0: Disable reset on error.1: Enable reset on error.Reserved
Startup phase in which DONE pin is released.(001,010,011,100,101,110)
Stall in this startup phase until DCM or PLL lock is asserted. (001,010,011,100,101,110,111
Startup phase in which I/Os switch from 3-state to user design.
(000
Startup phase in which the global write enable is asserted.(000
BitGen Default
00110111000
000
00
COR2RESET_ON_ERROR15
0000100111 (No wait)
RESERVEDDONE_CYCLELCK_CYCLE
14:1211:98:6
GTS_CYCLE5:3101
GWE_CYCLE2:0110
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Configuration Packets
Suspend Register (PWRDN_REG)
Table 5-37:
FieldRESERVEDEN_EYES
Power-Down Register DescriptionBit Index
1514
Reserved.
Enable Multi-Pin Wake-Up.0: Disable Multi-Pin Wake-Up.1: Enable Multi-Pin Wake-Up.Reserved.
0: Suspend filter (300ns) on.1: Filter off.
0: No GSR pulse during return from Suspend.1: Generate GSR pulse during return from Suspend.Reserved.
0: Suspend is disabled.1: Suspend is enabled.
0: Use MCCLK for startup sequence initiated by power-up.
1: Use SSCLKSRC for startup sequence initiated by power-up.
010
Description
BitGen Default
RESERVEDFILTER_BEN_PGSR
13:654
0010_0010
00
RESERVEDEN_PWRDNKEEP_SCLK
320
Frame Length Register
Frame Length Register (FLR) is written with the length of a frame, as measured in 16-bit words, near the beginning of the configuration bitstream. FLR must be written before any FDR operation will work. It is not necessary to set the FLR more than once.The actual value written to FLR = Actual Frame Length.
Based on the segmentation scheme in Spartan-6 devices, the frame length for type0 (CLB, IOI, and special blocks) and type1 (block RAM) are fixed. The only block that needs a specified frame length is IOB.Table 5-38:
Bits[15:0]
Frame Length Register
FLR
xxxxxxxxxxxxxxxx
Multi-Frame Write Register
The Spartan-6 FPGA supports Multi-Frame Write (MFWR) for first-time configuration but does not support it during reconfiguration. The FPGA has to go through one power cycle or use PROGRAM_B to reset the chip before MFWR can be used.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
FPGA可编程逻辑器件芯片XC2S200-6FG456I中文规格书 - 图文
