back to ODT (RTT,nom) at the completion of the WRITE burst. If RTT,nom is disabled, theRTT,nom value will be High-Z. Special timing parameters must be adhered to when dy-namic ODT (RTT(WR)) is enabled: ODTLcnw, ODTLcnw4, ODTLcnw8, ODTH4, ODTH8,and tADC.
Dynamic ODT is only applicable during WRITE cycles. If ODT (RTT,nom) is disabled, dy-namic ODT (RTT(WR)) is still permitted. RTT,nom and RTT(WR) can be used independent ofone other. Dynamic ODT is not available during write leveling mode, regardless of thestate of ODT (RTT,nom). For details on dynamic ODT operation, refer to the DynamicODT section of the data sheet for more details.
Mode Register 3 (MR3)
The mode register 3 (MR3) controls additional functions and features not available inthe other mode registers. Currently defined is the MULTIPURPOSE REGISTER (MPR).This function is controlled via the bits shown in Figure 58 (page 148). The MR3 is pro-grammed via the LOAD MODE command and retains the stored information until it isprogrammed again or until the device loses power. Reprogramming the MR3 registerwill not alter the contents of the memory array, provided it is performed correctly. TheMR3 register must be loaded when all banks are idle and no data bursts are in progress,and the controller must wait the specified time tMRD and tMOD before initiating a sub-sequent operation.
Figure 58: Mode Register 3 (MR3) Definition
BA2BA1BA0A13A12A11A10A9A8A7A6A5A4A3A2A1A0Address bus16011514131211109876543210110101010101010101010101MPR MPR_RFMode register 3 (MR3)M15M1400110101Mode Register Mode register set (MR0)Mode register set 1 (MR1)Mode register set 2 (MR2)Mode register set 3 (MR3)M201MPR EnableNormal DRAM operations2Dataflow from MPRM1M000110101MPR READ FunctionPredefined pattern3ReservedReservedReservedNotes:
1.MR3[16 and 13:3] are reserved for future use and must all be programmed to 0.
2.When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored.3.Intended to be used for READ synchronization.
MULTIPURPOSE REGISTER (MPR)
The MULTIPURPOSE REGISTER function is used to output a predefined system timingcalibration bit sequence. Bit 2 is the master bit that enables or disables access to theMPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basicconcept of the multipurpose register is shown in Figure 59 (page 149).
If MR3[2] is a 0, then the MPR access is disabled, and the DRAM operates in normalmode. However, if MR3[2] is a 1, then the DRAM no longer outputs normal read databut outputs MPR data as defined by MR3[0, 1]. If MR3[0, 1] is equal to 00, then a prede-fined read pattern for system calibration is selected.
1Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 3 (MR3)
To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1. Prior to issu-ing the MRS command, all banks must be in the idle state (all banks are precharged,and tRP is met). When the MPR is enabled, any subsequent READ or RDAP commandsare redirected to the multipurpose register. The resulting operation when either a READor a RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (see Table 75 (page 150)). When the MPR is enabled, only READ or RDAP commands are al-lowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] = 0).Power-down mode, self refresh, and any other nonREAD/RDAP commands are not al-lowed during MPR enable mode. The RESET function is supported during MPR enablemode.
Figure 59: Multipurpose Register (MPR) Block Diagram
Memory coreMR3[2] = 0 (MPR off)Multipurpose registerpredefined data for READsMR3[2] = 1 (MPR on)DQ, DM, DQS, DQS#Notes:
1.A predefined data pattern can be read out of the MPR with an external READ com-mand.
2.MR3[2] defines whether the data flow comes from the memory core or the MPR. When
the data flow is defined, the MPR contents can be read out continuously with a regularREAD or RDAP command.
Table 74: MPR Functional Description of MR3 Bits
MR3[2]MPR0MR3[1:0]MPR READ Function“Don’t Care”FunctionNormal operation, no MPR transactionAll subsequent READs come from the DRAM memory arrayAll subsequent WRITEs go to the DRAM memory arrayEnable MPR mode, subsequent READ/RDAP commands defined by bits 1 and21A[1:0](see Table 75 (page 150))MPR Functional Description
The MPR JEDEC definition enables either a prime DQ (DQ0 on a x4 and a x8; on a x16,DQ0 = lower byte and DQ8 = upper byte) to output the MPR data with the remainingDQs driven LOW, or for all DQs to output the MPR data. The MPR readout supports
1Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 3 (MR3)
fixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READlatencies and AC timings applicable, provided the DLL is locked as required.MPR addressing for a valid MPR read is as follows:
?A[1:0] must be set to 00 as the burst order is fixed per nibble?A2 selects the burst order:
–BL8, A2 is set to 0, and the burst order is fixed to 0, 1, 2, 3, 4, 5, 6, 7
?For burst chop 4 cases, the burst order is switched on the nibble base along with thefollowing:
–A2 = 0; burst order = 0, 1, 2, 3–A2 = 1; burst order = 4, 5, 6, 7
Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) isassigned to MSB
A[9:3] are a “Don’t Care”A10 is a “Don’t Care”A11 is a “Don’t Care”
A12: Selects burst chop mode on-the-fly, if enabled within MR0A13 is a “Don’t Care”
BA[2:0] are a “Don’t Care”
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MPR Register Address Definitions and Bursting Order
The MPR currently supports a single data format. This data format is a predefined readpattern for system calibration. The predefined pattern is always a repeating 0–1 bit pat-tern.
Examples of the different types of predefined READ pattern bursts are shown in the fol-lowing figures.
Table 75: MPR Readouts and Burst Order Bit Mapping
MR3[2]1MR3[1:0]00FunctionREAD predefined patternfor system calibrationBurstLengthBL8BC4BC4101RFUn/an/an/a110RFUn/an/an/aReadA[2:0]000000100n/an/an/an/an/an/aBurst Order and Data PatternBurst order: 0, 1, 2, 3, 4, 5, 6, 7Predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1Burst order: 0, 1, 2, 3Predefined pattern: 0, 1, 0, 1Burst order: 4, 5, 6, 7Predefined pattern: 0, 1, 0, 1n/an/an/an/an/an/a
MEMORY存储芯片MT46V128M4CY-6 J中文规格书
