Chapter 1: Overview
Related InformationXP IOB ResourcesHD IOB Resources
Supply Voltages and Dedicated SelectIO Pins
VCCO
The VCCO supply is the primary power supply for drivers and termination. The XP IOB SupportedStandards section includes tables that outline the VCCO requirements for each of the supportedI/O standards, and illustrate the VCCO requirements for inputs and outputs including the optionalinternal differential termination circuit. All VCCO pins for a given XP or HD I/O bank must beconnected to the same external voltage supply on the board, and as a result, all of the I/O withina given I/O bank must be compatible with the same VCCO level. The VCCO voltage must matchthe requirements for the I/O standards that have been assigned to the I/O bank.
CAUTION! Incorrect VCCO voltages can result in loss of functionality or damage the device.
VCCAUX
The global auxiliary (VCCAUX) supply rail primarily provides power to the receive circuitry. In theI/O banks, VCCAUX is also used to power input buffer circuits for some of the I/O standards.
Additionally, the VCCAUX rail provides power to the differential input buffer circuits used for mostof the differential and VREF I/O standards.VCC_IO
VCC_IO is an internal supply for I/O banks. It supplies the digital portions and supporting logicSelectIO resources.IO_VR_700 / IO_VR_800
In XP I/O bank 700 and bank 800 (not present in all devices), there is an additional bank pin thatis used as a reference to calibrate internal on-die termination. The IO_VR pin must be externallyconnected to a 240Ω resistor on the PCB and pulled up to the bank VCCO voltage. See CalibratedTermination (Digitally Controlled Impedance). HD I/O banks do not support calibratedtermination and thus no equivalent pin or reference resistor is required on HD I/O banks.
IMPORTANT! The IO_VR_700 and IO_VR_800 pins (not available on all devices) must have an external240Ω resistor tied to VCCO_700 and VCCO_800 respectively. These pins are dedicated and can not beused as user I/O. All designs MUST populate these pins appropriately, regardless of the I/O standards usedin a design.
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Chapter 1: Overview
Power Supply Sequencing Requirements
The power supply requirements, including power-on and power-off sequencing, are described in Versal ACAP data sheets.
State of I/Os During and After Configuration
During configuration, I/O drivers are tristated in all banks. During configuration (until the
applications settings take over), all XP I/O banks use the default IOSTANDARD = LVCMOS15,SLEW = FAST, and DRIVE = 12 mA setting. The corresponding setting in HD I/O banks is
IOSTANDARD = LVCMOS25, SLEW = FAST, and DRIVE = 12 mA. The PUDC_B input pin can beuse to enable internal pull-ups during configuration. After configuration, the unused I/Os havetristated drivers, and the pads are weakly pulled-down.
Note: This manual applies only to PL-based HD and XP SelectIO resources. Multiplexed I/O are describedin Versal ACAP Technical Reference Manual (AM011).
I/O Banking Rules
In the Versal architecture, XP and HD IOBs use the bank VCCO supply for drivers, on-die biasing,on-die termination, and the receive block. Because of the dependency on VCCO, all outputs andmany inputs must operate at a specific VCCO level making it is a dominant factor in determiningthe IOSTANDARDS that can reside in the same bank.
Rules for Combining Standards Different Standards in the Same Bank
?VCCO levels must be compatible for all inputs and outputs in the same HD or XP I/O bank?INTERNAL_VREF levels must be compatible for all inputs in the same HD or XP I/O bank
Note: In Versal devices, all single-ended input and all output (single-ended and differential) IOSTANDARDShave a required VCCO level. Only the differential inputs that do not use ODT, PULLTYPE, or DIFF_TERMcan reside in multiple VCCO domains. Although a differential input may be compatible with multiple Vccodomains, it is important to note that data sheet input specifications are impacted by the Vcco level andcompatibility should verified when selecting a Vcco level.
The supported standards and their associated VCCO and INTERNAL_VREF requirements aredescribed in the XP and HD IOB supported sections.Related InformationXP IOB Supported StandardsHD IOB Supported Standards
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Differences from Previous Generations
Versal? ACAPs have several important feature enhancements as well as updates to existingfeatures.
XP XPHY
The following table summarizes the key differences between the UltraScale? architecture PHYand the Versal? architecture XPHY.
Table 1: UltraScale Architecture PHY and Versal Architecture XPHY Key Differences
Function
NIBBLESLICEs per nibbleNibbles per bankSerializationDeserialization
Wizard required to access interfaceInput and output delays
Versal Architecture XPHY
69 (54 pins)8:1, 4:1, 2:11:8, 1:4, 1:2
Yes
625 ps (512 taps)
UltraScale Architecture PHY
6 or 78 (52 pins)8:1, 4:11:8, 1:4No
UltraScale devices: 1250 ps (512 taps)UltraScale+ devices: 1100 ps (512 taps)
Some of the other differences between the PHY architectures of UltraScale? and Versal devicesinclude the following:
?Receive FIFO bypass support for low-latency applications
?No NIBBLESLICE 0 (formerly called BITSLICE 0) instantiation requirements
?The IDELAYCTRL, ISERDES, OSERDES, RXTX_BITSLICE, RX_BITSLICE, TX_BITSLICE,BITSLICE_CONTROL, and RIU_OR UNISIM primitives are not supported?The XP IOL resources are independent of the XPHY. Only one or the other can be used at atime.?Programmable logic control ports are shared between input and output delays through a delayselect port?Some XPIO banks (typically located on the corner of the device) have pins that have limitedfunction and can only be used for DDR memory controller functionality. See the Versal ACAPPackaging and Pinouts Architecture Manual (AM013) for specific pin information. Also see theVersal Architecture and Product Data Sheet: Overview (DS950).?QBC and DBC functionality has been split into two parts: Strobes now enter on XCC pins,while inter-nibble and inter-byte clocking capabilities are determined by the nibble.?The PHY can only be constructed by using the Advanced IO Wizard together with theAdvanced I/O Planner (see Advanced I/O Wizard LogiCORE IP Product Guide (PG320)).
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FPGA可编程逻辑器件芯片XC2V1000-5FG896C中文规格书
