2、并行数据转串行数据模块（xulie.v） module xulie(DIN8,CLK,CLR,DIN); input CLK,CLR; input [7:0]DIN8; output DIN;
reg [2:0] cur_state,next_state; reg DIN; parameter s0 = 3'b000, s1 = 3'b001, s2 = 3'b010, s3 = 3'b011, s4 = 3'b100, s5 = 3'b101, s6 = 3'b110, s7 = 3'b111;
always @ (posedge CLK or posedge CLR) begin if(CLR) cur_state <= s0; else cur_state <= next_state; end
always @ (cur_state or DIN8 or DIN ) begin case (cur_state) s0 : begin DIN <= DIN8[7]; next_state <= s1; end s1 : begin DIN <= DIN8[6]; next_state <= s2; end s2 : begin DIN <= DIN8[5]; next_state <= s3; end s3 : begin DIN <= DIN8[4]; next_state <= s4; end s4 : begin DIN <= DIN8[3]; next_state <= s5; end s5 : begin DIN <= DIN8[2];
next_state <= s6; end s6 : begin DIN <= DIN8[1]; next_state <= s7; end s7 : begin DIN <= DIN8[0]; next_state <= s0; end default : begin DIN <= 1'b0; next_state <= s0; end endcase end endmodule
2.1并行数据转串行数据综合
2.2并行数据转串行数据仿真
3、串行检测模块（schk.v） module schk(DIN,CLK,CLR,AB); input DIN,CLK,CLR; output[3:0] AB;
reg [3:0] cur_state,next_state; reg [3:0] AB=4'b0000;
parameter idle = 4'b0000, s1 = 4'b0001, s2 = 4'b0010, s3 = 4'b0011, s4 = 4'b0100, s5 = 4'b0101, s6 = 4'b0110, s7 = 4'b0111, s8 = 4'b1000;
always @(posedge CLK or posedge CLR) begin if(CLR) cur_state <= idle; else cur_state <= next_state; end
always @(cur_state or DIN) begin case(cur_state) idle: begin AB <= 4'b1011; if(DIN==1'b0) next_state <= s1; else next_state <= s1;
end s1: begin AB <= 4'b1011; if(DIN==1'b1) next_state <= s2; else next_state <= s1; end s2: begin AB <= 4'b1011; if(DIN==1'b1) next_state <= s3; else next_state <= s1; end s3: begin AB <= 4'b1011; if(DIN==1'b1) next_state <= s3; else next_state <= s1; end s4: begin AB <= 4'b1011; if(DIN==1'b1) next_state <= s5; else next_state <= s1; end s5: begin AB <= 4'b1011; if(DIN==1'b0) next_state <= s6; else next_state <= idle; end s6: begin AB <= 4'b1011; if(DIN==1'b0) next_state <= s7; else next_state <= s2; end s7: begin if(DIN==1'b0) begin AB <= 4'b1010; next_state <= s8; end else begin next_state <= s2; AB <= 4'b1011; end end s8: begin AB <= 4'b1011; if(DIN==1'b1) next_state <= s2;
else next_state <= s1; end default : next_state <= idle; endcase end endmodule
3.1 串行检测模块综合仿真
4、xulieqi组合模块
module xulieqi(DIN8,CLK,CLR,Q); input CLK,CLR; input [7:0] DIN8; output [6:0] Q; wire [3:0] AB;
xulie u1 (.DIN8(DIN8),.CLK(CLK),.CLR(CLR),.DIN(DIN)); schk u2 (.CLR(CLR),.DIN(DIN),.AB(AB)); decled7s u3 (.AB(AB),.Q(Q)); endmodule
FPGA用状态机实现序列检测器的设计
