DS099 (v3.1) June 27, 2013Product Specification
DC Electrical Characteristics
In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as follows:?
Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristicsof other families. Values are subject to change. Although speed grades with this designation are considered relativelystable and conservative, some under-reporting might still occur. Use as estimates, not for production.
Preliminary: Based on complete early silicon characterization. Devices and speed grades with this designation areintended to give a better indication of the expected performance of production silicon. The probability of under-reporteddelays is greatly reduced compared to Advance data. Use as estimates, not for production.
Production: These specifications are approved only after silicon has been characterized over numerous productionlots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes.Parameter values are considered stable with no future changes expected.
Production-quality systems must only use FPGA designs compiled with a Production status speed file. FPGA designsusing a less mature speed file designation should only be used during system prototyping or preproduction qualification.FPGA designs with speed files designated as Advance or Preliminary should not be used in a production-qualitysystem.
Whenever a speed file designation changes, as a device matures toward Production status, rerun the latest Xilinx ISE? software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software updates.
All parameter limits are representative of worst-case supply voltage and junction temperature conditions. The following applies unless otherwise noted: The parameter values published in this module apply to all Spartan?-3 devices. AC and DC characteristics are specified using the same numbers for both commercial and industrial grades. All parameters representing voltages are measured with respect to GND.
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Mask and Fab Revisions
Some specifications list different values for one or more mask or fab revisions, indicated by the device top marking (see Package Marking, page5). The revision differences involve the power ramp rates, differential DC specifications, and DCM characteristics. The most recent revision (mask rev E and GQ fab/geometry code) is errata-free with improved specifications than earlier revisions.
Mask rev E with fab rev GQ has been shipping since 2005 (see XCN05009) and has been 100% of Xilinx Spartan-3 device shipments since 2006. SCD 0974 was provided to ensure the receipt of the rev E silicon, but it is no longer needed. Parts ordered under the SCD appended “0974” to the standard part number. For example, “XC3S50-4VQ100C” became “XC3S50-4VQ100C0974”.
Table 28:Absolute Maximum Ratings
SymbolVCCINTVCCAUXVCCOVREFVIN
Description
Internal supply voltage relative to GNDAuxiliary supply voltage relative to GNDOutput driver supply voltage relative to GNDInput reference voltage relative to GNDVoltage applied to all User I/O pins and Dual-Purpose pins relative to GND(2,4)Voltage applied to all Dedicated pins relative to GND(3)
ConditionsMin–0.5–0.5–0.5–0.5
Max1.323.003.75VCCO+0.5
4.44.3VCCAUX + 0.5
UnitsVVVVVV
Driver in a
high-impedance state
CommercialIndustrialAll temp. ranges
–0.95–0.85–0.5
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 41:System-Synchronous Pin-to-Pin Setup and Hold Times for the IOB Input Path (Cont’d)
Speed Grade
SymbolTPHFD
Description
Conditions
DeviceXC3S50XC3S200XC3S400XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
Notes:
1.2.3.
The numbers in this table are tested using the methodology presented in Table48 and are based on the operating conditions set forth inTable32 and Table35.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the dataInput. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table44. If this is true of the data Input, add theappropriate Input adjustment from the same table.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the dataInput. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table44. If this is true of the data Input, subtract theappropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s activeedge.
DCM output jitter is included in all measurements.
-5Min–0.98–0.40–0.27–1.19–1.43–2.33–2.47–2.66
-4Min–0.93–0.35–0.22–1.14–1.38–2.28–2.42–2.61
Unitsnsnsnsnsnsnsnsns
When writing to IFF, the time from LVCMOS25(3), the active transition at the Global IOBDELAY = IFD, Clock pin to the point when data without DCMmust be held at the Input pin. The DCM is not in use. The Input Delay is programmed.
4.
Table 42:Setup and Hold Times for the IOB Input Path
Speed Grade
SymbolSetup Times
TIOPICK
Time from the setup of data at the Input pin LVCMOS25(2),
to the active transition at the ICLK input of IOBDELAY = NONEthe Input Flip-Flop (IFF). No Input Delay is programmed.
XC3S50XC3S200XC3S400XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
TIOPICKD
Time from the setup of data at the Input pin LVCMOS25(2), to the active transition at the IFF’s ICLK IOBDELAY = IFDinput. The Input Delay is programmed.
XC3S50XC3S200XC3S400XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
1.651.371.371.651.651.651.731.824.394.764.635.025.406.687.167.33
1.891.571.571.891.891.891.992.095.045.475.325.766.207.688.248.42
nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsns
DescriptionConditionsDevice-5Min
-4Min
Units
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 46:Timing for the IOB Three-State Path
Speed Grade
Symbol
Description
Conditions
Device
-5Max(3)
Synchronous Output Enable/Disable TimesTIOCKHZ
Time from the active transition at the OTCLK input of the Three-state Flip-Flop (TFF) to when the Output pin enters the high-impedance state
Time from the active transition at TFF’s OTCLK input to when the Output pin drives valid data
LVCMOS25, 12mA output drive, Fast slew rate
All
0.74
0.85
ns
-4Max(3)
Units
TIOCKON(2)
All0.720.82ns
Asynchronous Output Enable/Disable TimesTGTS
Time from asserting the Global Three State LVCMOS25, 12mA (GTS) net to when the Output pin enters the output drive, Fast slew high-impedance staterate
XC3S200
XC3S400XC3S50XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
7.718.38
8.879.63
nsns
Set/Reset TimesTIOSRHZ
Time from asserting TFF’s SR input to when LVCMOS25, 12mA
output drive, Fast slew the Output pin enters a high-impedance
ratestate
Time from asserting TFF’s SR input at TFF
to when the Output pin drives valid data
All
1.55
1.78
ns
TIOSRON(2)
XC3S200XC3S400XC3S50XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
2.242.91
2.573.34
nsns
Notes:
1.2.3.
The numbers in this table are tested using the methodology presented in Table48 and are based on the operating conditions set forth inTable32 and Table35.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from Table47.For minimums, use the values reported by the Xilinx timing analyzer.
Table 47:Output Timing Adjustments for IOB
Add the Adjustment Below
Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the
Following Signal Standard (IOSTANDARD)
-5
Speed Grade
-4
Units
Single-Ended StandardsGTLGTL_DCIGTLPGTLP_DCIHSLVDCI_15HSLVDCI_18
00.130.030.231.510.81
0.020.150.040.271.740.94
nsnsnsnsnsns
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 47:Output Timing Adjustments for IOB (Cont’d)
Add the Adjustment Below
Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the
Following Signal Standard (IOSTANDARD)
-5
LVCMOS18
Slow
2 mA4 mA6 mA8 mA12 mA16 mA
Fast
2 mA4 mA6 mA8 mA12 mA16 mA
LVDCI_18LVDCI_DV2_18LVCMOS25
Slow
2 mA4 mA6 mA8 mA12 mA16 mA24 mA
Fast
2 mA4 mA6 mA8 mA12 mA16 mA24 mA
LVDCI_25LVDCI_DV2_25
5.493.452.842.622.112.072.501.150.960.870.790.760.810.676.434.153.382.992.532.502.223.271.870.320.190–0.02–0.040.270.16
Speed Grade
-46.313.973.263.012.432.382.881.321.101.010.910.870.940.777.394.773.893.442.912.872.553.762.150.370.220–0.01–0.020.310.19
nsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsnsUnits
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XCZU15EG-1FFVC900I中文规格书 - 图文
