STM8S003K3 STM8S003F3
Value line, 16 MHz STM8S 8-bit MCU, 8 Kbytes Flash, 128 bytes
data EEPROM, 10-bit ADC, 3 timers, UART, SPI, I2C
Interrupt management
Nested interrupt controller with 32 interrupts
·· Up to 27 external interrupts on 6 vectors
LQFP32 7x7
TSSOP20
UFQFPN20 3x3
Timers
Advanced control timer: 16-bit, 4 CAPCOM
Features
Core
16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline
·channels, 3 complementary outputs, dead-time ·· 8-bit basic timer with 8-bit prescaler · Auto wake-up timer · Window watchdog and independent watchdog
Communications interfaces
UART with clock output for synchronous
operation, Smartcard, IrDA, LIN master mode insertion and flexible synchronization
, or PWM) with 3 CAPCO 16-bit generalOC·
· Extended instruction set
Memories
Program memory: 8 Kbytes Flash; data retention 20 years at 55 °C after 100 cycles
· · RAM:memory: 128 bytes of true data EEPROM; · endurance up to 100 000 write/erase cycles
Clock, reset and supply management 2.95 to 5.5 V operating voltage
clock control, 4 master clock sources:
·
· SPI interface up to 8 Mbit/s
· I C interface up to 400 Kbit/s Analog to digital converter (ADC)
2·
10-bit, ±1 LSB ADC with up to 5 multiplexed channels, scan mode and analog watchdog
·· Flexiblepower crystal resonator oscillator - management: ·Power I/Os
Up to 28 I/Os on a 32-pin package including 21 high sink outputs
(wait, active-halt, halt)
Development support
- Switch-off peripheral clocks individually Embedded single wire interface module (SWIM)
for fast on-chip programming and non intrusive
Permanentlyactive,consumptionpower-on· ·debugging reset
·
· Highly robust I/O design, immune against current
- Low power modes
June 2012
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Contents
STM8S003K3 STM8S003F3
Contents
1 Introduction ............................................................................................................. 2 Description .............................................................................................................. 3 Block diagram ......................................................................................................... 4 Product overview ..................................................................................................
4.1 Central processing unit STM8 .................................................................................... 4.2 Single wire interface module (SWIM) and debug module (DM) ................................. 4.3 Interrupt controller ...................................................................................................... 4.4 Flash program memory and data EEPROM ............................................................... 4.5 Clock controller ........................................................................................................... 4.6 Power management ................................................................................................... 4.7 Watchdog timers ......................................................................................................... 4.8 Auto wakeup counter .................................................................................................. 4.9 Beeper ....................................................................................................................... 4.10 TIM1 - 16-bit advanced control timer ........................................................................ 4.11 TIM2 - 16-bit general purpose timer ......................................................................... 4.12 TIM4 - 8-bit basic timer ............................................................................................. 4.13 Analog-to-digital converter (ADC1) ........................................................................... 4.14 Communication interfaces ........................................................................................
4.14.1 UART1 .............................................................................................. 4.14.2 SPI .................................................................................................... 4.14.3 I2C .....................................................................................................
7
8 9 10
10 10 11 11 12 13 13 14 14 14 15 15 15 16 16 17 17
5 Pinout and pin description ..................................................................................
5.1 STM8S003K3 LQFP32 pinout and pin description ..................................................... 5.2 STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description ..............................
5.2.1 STM8S003F3 TSSOP20 pinout and pin description ........................... 5.2.2 STM8S003F3 UFQFPN20 pinout ....................................................... 5.2.3 STM8S003F3 TSSOP20/UFQFPN20 pin description .........................
5.3 Alternate function remapping ......................................................................................
18
18 21 21 22 22 24
6 Memory and register map .................................................................................... 25
6.1 Memory map ............................................................................................................... 25 6.2 Register map .............................................................................................................. 26
6.2.1 I/O port hardware register map ........................................................... 26 6.2.2 General hardware register map......................................................... 27 6.2.3 CPU/SWIM/debug module/interrupt controller registers.................... 36
7 Interrupt vector mapping ..................................................................................... 39 8 Option bytes .......................................................................................................... 41
8.1 Alternate function remapping bits ...............................................................................
43
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Contents
9 Electrical characteristics .....................................................................................
9.1 Parameter conditions ..................................................................................................
9.1.1 Minimum and maximum values .......................................................... 9.1.2 Typical values ...................................................................................... 9.1.3 Typical curves ..................................................................................... 9.1.4 Loading capacitor ................................................................................ 9.1.5 Pin input voltage ..................................................................................
9.2 Absolute maximum ratings ......................................................................................... 9.3 Operating conditions ...................................................................................................
9.3.1 VCAP external capacitor ..................................................................... 9.3.2 Supply current characteristics ............................................................. 9.3.3 External clock sources and timing characteristics .............................. 9.3.4 Internal clock sources and timing characteristics ................................ 9.3.6 I/O port pin characteristics .................................................................. 9.3.7 Reset pin characteristics ..................................................................... 9.3.8 SPI serial peripheral interface ............................................................. 9.3.9 I C interface characteristics ................................................................ 80 9.3.10 10-bit ADC characteristics .................................................................
2
46
46 46 46 46 46 46 47 49 50 51 60 62 66 74 77 81
9.3.5 Memory characteristics ....................................................................... 64
9.3.11 EMC characteristics .......................................................................... 85
10 Package information ..........................................................................................
10.1 32-pin LQFP package mechanical data ................................................................... 10.2 20-pin TSSOP package mechanical data ................................................................. 10.3 20-lead UFQFPN package mechanical data ............................................................
89
89 90 92
11 Thermal characteristics ......................................................................................
11.1 Reference document ................................................................................................ 11.2 Selecting the product temperature range .................................................................
94
94 94
12 Ordering information .......................................................................................... 13 STM8 development tools ...................................................................................
13.1 Emulation and in-circuit debugging tools .................................................................. 13.2 Software tools ...........................................................................................................
13.2.1 STM8 toolset ..................................................................................... 13.2.2 C and assembly toolchains ...............................................................
13.3 Programming tools ...................................................................................................
96 97
97 97 98 98 98
14 Revision history ..................................................................................................
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List of tables
STM8S003K3 STM8S003F3
List of tables
Table 1. STM8S003xx value line features ............................................................................................... Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers ................................. Table 3. TIM timer features ................................................................................................................... Table 4. Legend/abbreviations for pinout tables.................................................................................. Table 5. LQFP32 pin description ........................................................................................................... Table 6. STM8S003F3 pin description .................................................................................................. Table 7. I/O port hardware register map ............................................................................................... Table 8. General hardware register map.............................................................................................. Table 9. CPU/SWIM/debug module/interrupt controller registers........................................................ Table 10. Interrupt mapping .................................................................................................................. Table 11. Option bytes.......................................................................................................................... Table 12. Option byte description .......................................................................................................... Table 13. STM8S003K3 alternate function remapping bits for 32-pin devices ..................................... Table 14. STM8S003F3 alternate function remapping bits for 20-pin devices ..................................... Table 15. Voltage characteristics .......................................................................................................... Table 16. Current characteristics .......................................................................................................... Table 17. Thermal characteristics ......................................................................................................... Table 18. General operating conditions ................................................................................................ Table 19. Operating conditions at power-up/power-down ..................................................................... Table 20. Total current consumption with code execution in run mode at VDD = 5 V ............................ Table 21. Total current consumption with code execution in run mode at VDD = 3.3 V ......................... Table 22. Total current consumption in wait mode at VDD = 5 V ........................................................... Table 23. Total current consumption in wait mode at VDD = 3.3 V ........................................................ Table 24. Total current consumption in active halt mode at VDD = 5 V ................................................. Table 25. Total current consumption in active halt mode at VDD = 3.3 V .............................................. Table 26. Total current consumption in halt mode at VDD = 5 V ............................................................ Table 27. Total current consumption in halt mode at VDD = 3.3 V ......................................................... Table 28. Wakeup times ........................................................................................................................ Table 29. Total current consumption and timing in forced reset state ................................................... Table 30. Peripheral current consumption ............................................................................................ Table 31. HSE user external clock characteristics ................................................................................ Table 32. HSE oscillator characteristics ................................................................................................ Table 33. HSI oscillator characteristics ................................................................................................. Table 34. LSI oscillator characteristics .................................................................................................. Table 35. RAM and hardware registers ................................................................................................. Table 36. Flash program memory and data EEPROM .......................................................................... Table 37. I/O static characteristics ........................................................................................................ Table 38. Output driving current (standard ports) ................................................................................. Table 39. Output driving current (true open drain ports) ....................................................................... Table 40. Output driving current (high sink ports) ................................................................................. Table 41. NRST pin characteristics ....................................................................................................... Table 42. SPI characteristics .................................................................................................................
2 Table 43. I C characteristics ................................................................................................................. 80
Table 44. ADC characteristics ............................................................................................................... Table 45. ADC accuracy with RAIN < 10 kΩ , VDD= 5 V........................................................................ Table 46. ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V............................................................. Table 47. EMS data ...............................................................................................................................
8 13 15 18 19 22 26 27 36 39 99 41 43 44 47 47 48 49 50 51 52 53 53 54 54 55 55 56 57 57 60 61 62 64 64 65 66 68 68 69 74 78 82 82 83 86
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List of tables
86 87 88 89 91 92 94 99
Table 48. EMI data ................................................................................................................................ Table 49. ESD absolute maximum ratings ............................................................................................ Table 50. Electrical sensitivities ............................................................................................................ Table 51. 32-pin low profile quad flat package mechanical data ........................................................... Table 52. 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data ........................................................ Table 53. 20-lead ultra thin fine pitch quad flat no-lead package (3x3) mechanical data ..................... Table 54. Thermal characteristics ......................................................................................................... Table 55. Document revision history .....................................................................................................
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List of figures
STM8S003K3 STM8S003F3
List of figures
Figure 1. Block diagram .......................................................................................................................... Figure 2. Flash memory organization ................................................................................................... Figure 3. STM8S003K3 LQFP32 pinout ............................................................................................... Figure 4. STM8S003F3 TSSOP20 pinout ............................................................................................. Figure 5. STM8S003F3 UFQFPN20-pin pinout .................................................................................... Figure 6. Memory map .......................................................................................................................... Figure 7. Pin loading conditions ............................................................................................................ Figure 8. Pin input voltage .................................................................................................................... Figure 9. fCPUmax versus VDD ............................................................................................................... Figure 10. External capacitor CEXT ...................................................................................................... Figure 11. Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz ............................................ Figure 12. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V ................................................... Figure 13. Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz ................................................................ Figure 14. Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz ............................................. Figure 15. Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V .................................................... Figure 16. Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz ................................................................ Figure 17. HSE external clock source ................................................................................................... Figure 18. HSE oscillator circuit diagram .............................................................................................. Figure 19. Typical HSI frequency variation vs VDD @ 4 temperatures ................................................. Figure 20. Typical LSI frequency variation vs VDD @ 4 temperatures .................................................. Figure 21. Typical VIL and VIH vs VDD @ 4 temperatures ..................................................................... Figure 22. Typical pull-up resistance vs VDD @ 4 temperatures ........................................................... Figure 23. Typical pull-up current vs VDD @ 4 temperatures ................................................................ Figure 24. Typ. VOL @ VDD = 5 V (standard ports) ............................................................................... Figure 25. Typ. VOL @ VDD = 3.3 V (standard ports) ............................................................................ Figure 26. Typ. VOL @ VDD = 5 V (true open drain ports) ..................................................................... Figure 27. Typ. VOL @ VDD = 3.3 V (true open drain ports) .................................................................. Figure 28. Typ. VOL @ VDD = 5 V (high sink ports) ............................................................................... Figure 29. Typ. VOL @ VDD = 3.3 V (high sink ports) ............................................................................ Figure 30. Typ. VDD - VOH@ VDD = 5 V (standard ports) ...................................................................... Figure 31. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) .................................................................. Figure 32. Typ. VDD - VOH@ VDD = 5 V (high sink ports) ...................................................................... Figure 33. Typ. VDD - VOH@ VDD = 3.3 V (high sink ports) ................................................................... Figure 34. Typical NRST VIL and VIH vs VDD @ 4 temperatures .......................................................... Figure 35. Typical NRST pull-up resistance vs VDD @ 4 temperatures ................................................ Figure 36. Typical NRST pull-up current vs VDD @ 4 temperatures ..................................................... Figure 37. Recommended reset pin protection ..................................................................................... Figure 38. SPI timing diagram - slave mode and CPHA = 0 ................................................................. Figure 39. SPI timing diagram - slave mode and CPHA = 1 ................................................................. Figure 40. SPI timing diagram - master mode(1) ..................................................................................
2 Figure 41. Typical application with I C bus and timing diagram ........................................................... 84
Figure 42. ADC accuracy characteristics .............................................................................................. Figure 43. Typical application with ADC ............................................................................................... Figure 44. 32-pin low profile quad flat package (7 x 7) ......................................................................... Figure 45. 20-pin, 4.40 mm body, 0.65 mm pitch .................................................................................. Figure 46. 20-lead ultra thin fine pitch quad flat no-lead package outline (3x3) ................................... Figure 47. STM8S003x value line ordering information scheme ..........................................................
9 12 18 21 22 25 46 47 50 50 58 58 59 59 60 60 61 62 63 64 67 67 68 70 70 71 71 72 72 73 73 74 74 76 76 77 77 79 79 80 84 85 89 90 92 96
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Introduction
1 Introduction
This datasheet contains the description of the device features, pinout, electrical characteristics, mechanical data and ordering information.
For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016).
on programming, erasing and manualprotection of the For informationto theSTM8S Flash programming (PM0051).internal Flash memory
please refer
debug and SWIM (single wire interface module) refer For information on the protocol and debug module user manual (UM0470). to the STM8
SWIM communication
··· · For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044).
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Description
STM8S003K3 STM8S003F3
2 Description
The STM8S003x value line 8-bit microcontrollers feature 8 Kbytes Flash program memory, plus integrated true data EEPROM. The STM8S microcontroller family reference manual (RM0016) refers to devices in this family as low-density. They provide the following benefits: performance, robustness, and reduced system cost.
Device performance and robustness are ensured by integrated true data EEPROM supporting up to 100000 write/erase cycles, advanced core and peripherals made in a state-of-the art technology, a 16 MHz clock frequency, robust I/Os, independent watchdogs with separate clock source, and a clock security system.
The system cost is reduced thanks to high system integration level with internal clock oscillators, watchdog and brown-out reset.
Full documentation is offered as well as a wide choice of development tools.
Table 1: STM8S003xx value line features
Device Pin count
Maximum number of GPIOs (I/Os) Ext. interrupt pins Timer CAPCOM channels Timer complementary outputs A/D converter channels High sink I/Os
STM8S003K3 32 28 27 7 3 4 21
STM8S003F3 20 16 16 7 2 5 12 8K 1K 128 (1)
2
Low density Flash program memory (bytes) 8K RAM (bytes)
True data EEPROM (bytes) Peripheral set
1K 128 (1)
Multipurpose timer (TIM1), SPI, I C, UART window WDG,independent WDG, ADC, PWM timer (TIM2), 8-bit timer (TIM4)
(1) Without read-while-write capability.
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Block diagram
3
Block diagram
Figure 1: Block diagram
Reset block
Clock controller
XTAL 1-16 MHz
RC int. 16 MHz
Reset
PORReset
Single wiredebug interf. BOR
Detector
program Flash 128-byte
8-Kbyte
STM8 core
Clock to peripherals and coreRC int. 128 kHz
Window WDG
Debug/SWIMIndependent WDG
400 Kbit/s
8 Mbit/sI2C
SPIAddressanddatabus
data EEPROM
1-KbyteRAM Up to
LIN masterSPI emul.
UART116-bit advancedcontrol timer (TIM1)4 CAPCOMchannels +3complementaryoutputs
16-bit general purposetimer (TIM2)8-bit basic timer(TIM4)
Up to 5channels
ADC1
1/2/4 kHzbeep
Beeper
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AWU timer
Product overview
STM8S003K3 STM8S003F3
4
Product overview
The following section intends to give an overview of the basic features of the device functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual (RM0016).
4.1
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers Harvard architecture
·· 3-stage pipeline · 32-bit wide program memory bus - single cycle fetching for most instructions
and Y 16-bit index registers - enabling indexed addressing modes with or without offset · Xand read-modify-write type data manipulations · 8-bit accumulator · 24-bit program counter - 16-Mbyte linear memory space · 16-bit stack pointer - access to a 64 K-level stack · 8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
20 addressing modes
· · Indexed indirect addressing mode for look-up tables located anywhere in the address space · Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
80 instructions with 2-byte average instruction size
·· Standard data movement and logic/arithmetic functions · 8-bit by 8-bit multiplication · 16-bit by 8-bit and 16-bit by 16-bit division · Bit manipulation · Data transfer between stack and accumulator (push/pop) with direct stack access · Data transfer using the X and Y registers or direct memory-to-memory transfers
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Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time in-circuit debugging and fast memory programming.
STM8S003K3 STM8S003F3
Product overview
SWIM
Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module
The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real-time by means of shadow registers.
R/W to RAM and peripheral registers in real-time
·· R/W access to all resources by stalling the CPU · Breakpoints on all program-memory instructions (software breakpoints) · Two advanced breakpoints, 23 predefined configurations
4.3
Interrupt controller
· Nested interrupts with three software priority levels · 32 interrupt vectors with hardware priority · Up to 27 external interrupts on 6 vectors including TLI · Trap and reset interrupts
4.4 Flash program memory and data EEPROM
· 8 Kbytes of Flash program single voltage Flash memory
true areadata · 128 bytes ofbyte EEPROM
User option ·
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, the data EEPROM, and the option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to modify the content of the main program memory and data EEPROM, or to reprogram the device option bytes. A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to the figure below.
The size of the UBC is programmable through the UBC option byte, in increments of 1 page (64-byte block) by programming the UBC option byte in ICP mode. This divides the program memory into two areas: Main program memory: 8 Kbytes minus UBC
·· User-specific boot code (UBC): Configurable up to 8 Kbytes
The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
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Product overview
STM8S003K3 STM8S003F3
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines.
Figure 2: Flash memory organization
Option bytes Data EEPROM (128 bytes) UBC area Remains write protected during IAP Programmable area from 64 bytes(1 page) up to 8 Kbytes (in 1 page steps) Low density Flash program memory (8 Kbytes) Program memory area Write access possible for IAP
Read-out protection (ROP)
The read-out protection blocks reading and writing from/to the Flash program memory and the data EEPROM in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller.
4.5
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Clock controller
The clock controller distributes the system clock (fMASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.
Features
Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.
switching: Clock sources can signalbe changed on untilthe fly in newrun mode Safe clockconfiguration register. The clock is not safelyswitched the clock source
through a
is ready. The design guarantees glitch-free switching.
management: To reduce power orconsumption, Clockto the core, individual peripherals memory. the clock controller can stop the clock
··· · Master clock sources: Four different clock sources can be used to drive the master clock:
- 1-16 MHz high-speed external crystal (HSE)
- Up to 16 MHz high-speed user-external clock (HSE user-ext) - 16 MHz high-speed internal RC oscillator (HSI) - 128 kHz low-speed internal RC (LSI)
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Product overview
clock: After reset, the microcontroller restarts by default with an internal 2
· Startup(HSI/8). The prescaler ratio and clock source can be changed by the applicationMHz clock
· · Configurable main clock output (CCO): This outputs an external clock for use by the application.
Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Bit PCKEN17 PCKEN16 PCKEN15 PCKEN14
Peripheral Bit clock TIM1 Reserved TIM2 TIM4
PCKEN13 PCKEN12 PCKEN11 PCKEN10
Peripheral Bit clock UART1 Reserved SPI I C
2
program as soon as the code execution starts.
system (CSS): This feature can be enabled by software.If an andHSE clock Clock securitythe internal RC (16 MHz/8) is automatically selected by the CSS an
failure occurs,
interrupt can optionally be generated.
Peripheral Bit clock Reserved Reserved Reserved Reserved
PCKEN23 PCKEN22 PCKEN21 PCKEN20
Peripheral clock ADC AWU Reserved Reserved
PCKEN27 PCKEN26 PCKEN25 PCKEN24
4.6
Power management
For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources.
Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset.
mode with regulator on: In this mode, the CPU and peripheral clocks are up Active haltAn internal wakeup is generated at programmableintervals by the auto wakestopped.
unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.
modewith regulator off: This mode is the sameas activehalt with regulator Active haltthat the main voltage regulator is powered off, so thewake up time is slower.
on, except
In this mode the microcontroller uses least power. The CPU and peripheral Halt mode:stopped, the main voltage regulator is thepowered off. Wakeup is triggered by
clocks are
external event or reset.
····4.7 Watchdog timers
The watchdog system is based on two independent timers providing maximum security to the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset.
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Product overview
STM8S003K3 STM8S003F3
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application perfectly.
The application software must refresh the counter before time-out and during a limited time window.
A reset is generated in two situations:
1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 μs up to 64 ms.
2. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures.
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure
The IWDG time base spans from 60 μs to 1 s.
4.8
Auto wakeup counter
· Used for auto wakeup from active halt mode · Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock · LSI clock can be internally connected to TIM1 input capture channel 1 for calibration
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Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz.
The beeper output port is only available through the alternate function remap option bit AFR7.
4.10
TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver 16-bit up, down and up/down autoreload counter with 16-bit prescaler output
·
capture/compare channels (CAPCOM) configurable as input modecapture,· Four independentPWM generation (edge and center aligned mode) and single pulse
output compare, · Synchronization module to control the timer with external signals · Break input to force the timer outputs into a defined state · Three complementary outputs with adjustable dead time
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