2016年北邮数电实验报告

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数字电路与逻辑设计

. 实验报告

学院：电子工程学院 班级： ：

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学号： 班序号：

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目录

（一）实验名称及实验任务要求·························1 （二）模块端口说明及连接图····························2 1.1实验三(3)模块端口说明····························2 1.2实验三(3)连接图···································2 2.1实验四模块端口说明·······························2 2.2实验四连接图······································2 （三）原理图或VHDL代码································3 1.实验一(2)原理图·····································3 2.实验三(3)VHDL代码··································4 3.实验四VHDL代码····································7

（四）仿真波形··············································10 1.实验一(2)仿真波形····································10 2.实验三(3)仿真波形····································11 3.实验四仿真波形·······································11

（五）仿真波形分析··········································11 1.实验一(2)仿真波形分析································11

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2.实验三(3)仿真波形分析································11

3.实验四仿真波形分析····································11 （六）故障及问题分析·······································12 （七）总结和结论············································13

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（一）实验名称及实验任务要求 实验一

名称：QuartusII原理图输入法设计与实现

实验任务要求：EDA基础实验1（1）、（2）、（3）必做，选做VHDL实

现加法器。

实验二

名称：用VHDL设计与实现组合逻辑电路

实验任务要求：四人表决器、8421码转格雷码、数码管译码器（下载测试）。

实验三

名称：用VHDL设计与实现时序逻辑电路

实验任务要求：分频器、8421十进制计数器、将分频器/8421十进制计数器/数码管译码器3个电路进行连接并下载。

实验四

名称：用VHDL设计与实现相关电路

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