Normal Mode
Normal mode is suitable for general logic applications and combinational functions. In this mode, up to eight data inputs from the LAB local interconnect are inputs to the combinational logic. Normal mode allows two functions to be implemented in one Arria II ALM, or a single function of up to six inputs. The ALM can support certain combinations of completely independent functions and various combinations of functions that have common inputs.
Figure2–7 shows the supported LUT combinations in normal mode.
Figure2–7.ALM in Normal Mode (Note1)
dataf0datae0datacdataadatabdataddatae1dataf14-InputLUTcombout0dataf0datae0datacdataadatab5-InputLUTcombout04-InputLUTcombout1dataddatae1dataf15-InputLUTcombout1dataf0datae0datacdataadatab5-InputLUTcombout0dataddatae1dataf1dataf0datae0dataadatabdatacdatad6-InputLUTcombout03-InputLUTcombout1dataf0datae0datacdataadatab5-InputLUTcombout0dataf0datae0dataadatabdatacdatad6-InputLUTcombout0dataddatae1dataf14-InputLUTcombout1datae1dataf16-InputLUTcombout1Note to Figure2–7:
(1)Combinations of functions with fewer inputs than those shown are also supported. For example, combinations of functions with the following
number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, and 5 and 2.
Normal mode provides complete backward-compatibility with 4-input LUT architectures.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 2:Logic Array Blocks and Adaptive Logic Modules in ArriaII DevicesAdaptive Logic Modules
For the packing of two 5-input functions into one ALM, the functions must have at least two common inputs. The common inputs are dataa and datab. The combination of a 4-input function with a 5-input function requires one common input (either dataa or datab).
In the case of implementing two 6-input functions in one ALM, four inputs must be shared and the combinational function must be the same. In a sparsely used device, functions that could be placed in one ALM may be implemented in separate ALMs by the QuartusII software to achieve the best possible performance. As a device begins to fill up, the QuartusII software automatically utilizes the full potential of the ArriaII ALM. The QuartusII Compiler automatically searches for functions using common inputs or completely independent functions to be placed in one ALM to make efficient use of device resources. In addition, you can manually control resource usage by setting location assignments.
Any 6-input function can be implemented using inputs dataa, datab, datac, datad, and either datae0 and dataf0 or datae1 and dataf1. If datae0 and dataf0 are utilized, the output is driven to register0, and/or register0 is bypassed and the data drives out to the interconnect using the top set of output drivers (refer to Figure2–8). If datae1 and dataf1 are used, the output either drives to register1 or bypasses
register1 and drives to the interconnect using the bottom set of output drivers. The QuartusII Compiler automatically selects the inputs to the LUT. ALMs in normal mode support register packing.
Figure2–8.Input Function in Normal Mode (Note1)
dataf0datae0dataadatabdatacdataddatae1dataf1(2)labclkTo general orlocal routing6-InputLUTDQTo general orlocal routingreg0DQTo general orlocal routingreg1Notes to Figure2–8:
(1)If datae1 and dataf1 are used as inputs to a 6-input function, datae0 and dataf0 are available for register packing.(2)The dataf1 input is available for register packing only if the 6-input function is unregistered.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 2:Logic Array Blocks and Adaptive Logic Modules in ArriaII Devices
Adaptive Logic Modules
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 2:Logic Array Blocks and Adaptive Logic Modules in ArriaII DevicesAdaptive Logic Modules
Arithmetic Mode
Arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. The ALM in arithmetic mode uses two sets of two 4-input LUTs along with two dedicated full adders. The dedicated adders allow theLUTs to be available to perform pre-adder logic; therefore, each adder can add theoutput of two 4-input functions. The four LUTs share dataa and datab inputs. Asshown in Figure2–10, the carry-in signal feeds to adder0 and the carry-out from
adder0 feeds to the carry-in of adder1. The carry-out from adder1 drives to adder0 ofthe next ALM in the LAB. ALMs in arithmetic mode can drive out registered andunregistered versions of the adder outputs.
Figure2–10.ALM in Arithmetic Mode
carry_in
datae0
4-InputLUTDQadder0To general orlocal routingTo general orlocal routing
dataf0datacdatabdataa
4-InputLUTreg0dataddatae14-InputLUTadder1To general orlocal routing
DQTo general orlocal routing
4-InputLUTdataf1
carry_out
reg1In arithmetic mode, the ALM supports simultaneous use of the adder’s carry output along with combinational logic outputs. The adder output is ignored in this operation. Using the adder with combinational logic output provides resource savings of up to 50% for functions that can use this mode.
Arithmetic mode also offers clock enable, counter enable, synchronous up and down control, add and subtract control, synchronous clear, and synchronous load. The LAB local interconnect data inputs generate the clock enable, counter enable, synchronous up and down, and add and subtract control signals. These control signals are good candidates for the inputs that share the four LUTs in the ALM. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. These signals can also be individually disabled or enabled per register. The
QuartusII software automatically places any registers that are not used by the counter into other LABs.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 2:Logic Array Blocks and Adaptive Logic Modules in ArriaII Devices
Adaptive Logic Modules
Carry Chain
The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic mode. The two-bit carry select feature in ArriaII devices halves the propagation delay of carry chains within the ALM. Carry chains can begin in either the first ALM or the fifth ALM in a LAB. The final carry-out signal is routed to an ALM, where it is fed to local, row, or column interconnects. The QuartusII Compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. Parameterized functions such as LPM automatically take advantage of carry chains for the appropriate functions.
The QuartusII Compiler creates carry chains longer than 20 ALMs (10 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. To enhance fitting, a long carry chain runs vertically, allowing fast horizontal connections to TriMatrix memory and DSP blocks. A carry chain can continue as far as a full column.
To avoid routing congestion in one small area of the device when a high fan-in
arithmetic function is implemented, the LAB can support carry chains that only use either the top half or bottom half of the LAB before connecting to the next LAB. This leaves the other half of the ALMs in the LAB available for implementing narrower fan-in functions in normal mode. Carry chains that use the top five ALMs in the first LAB carry into the top half of the ALMs in the next LAB in the column. Carry chains that use the bottom five ALMs in the first LAB carry into the bottom half of the ALMs in the next LAB within the column. In every alternate LAB column, the top half can be bypassed; in the other MLAB columns, the bottom half can be bypassed.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
FPGA可编程逻辑器件芯片EP2AGX95EF29C6N中文规格书 - 图文
