FPGA可编程逻辑器件芯片XC2S50E-6TQ144I中文规格书 - 图文

Switching Characteristics

All Spartan-3 devices are available in two speed grades: –4 and the higher performance –5. Switching characteristics in this document may be designated as Advance, Preliminary, or Production. Each category is defined as follows:

Advance: These specifications are based on simulations only and are typically available soon after establishing FPGA specifications. Although speed grades with this designation are considered relatively stable and conservative, some under-reported delays may still occur.

Preliminary: These specifications are based on complete early silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting preliminary delays is greatly reduced compared to Advance data.

Production: These specifications are approved once enough production silicon of a particular device family member has been characterized to provide full correlation between speed files and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades.

Production-quality systems must use FPGA designs compiled using a Production status speed file. FPGAs designs using a less mature speed file designation may only be used during system prototyping or preproduction qualification. FPGA designs using Advance or Preliminary status speed files should never be used in a production-quality system.

Whenever a speed file designation changes, as a device matures toward Production status, rerun the Xilinx ISE software on the FPGA design to ensure that the FPGA design incorporates the latest timing information and software updates.

All specified limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise noted, the following applies: Parameter values apply to all Spartan-3 devices. All parameters representing voltages are measured with respect to GND.

Selected timing parameters and their representative values are included below either because they are important as general design requirements or they indicate fundamental device performance characteristics. The Spartan-3 FPGA v1.38 speed files are the original source for many but not all of the values. The v1.38 speed files are available in Xilinx Integrated Software Environment (ISE) software version 8.2i.

The speed grade designations for these files are shown in Table 39. For more complete, more precise, and worst-case data, use the values reported by the Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated to the simulation netlist.

Table 39: Spartan-3 FPGA Speed Grade Designations (ISE v8.2i or Later)

DeviceXC3S50XC3S200XC3S400XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000

-4, -5 (v1.38 andlater)

AdvancePreliminaryProduction-4, -5 (v1.37 andlater)

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: DC and Switching Characteristics

Table 46:Timing for the IOB Three-State Path

Speed Grade

Symbol

Description

Conditions

Device

-5Max(3)

Synchronous Output Enable/Disable TimesTIOCKHZ

Time from the active transition at the OTCLK input of the Three-state Flip-Flop (TFF) to when the Output pin enters the high-impedance state

Time from the active transition at TFF’s OTCLK input to when the Output pin drives valid data

LVCMOS25, 12mA output drive, Fast slew rate

All

0.74

0.85

ns

-4Max(3)

Units

TIOCKON(2)

All0.720.82ns

Asynchronous Output Enable/Disable TimesTGTS

Time from asserting the Global Three State LVCMOS25, 12mA (GTS) net to when the Output pin enters the output drive, Fast slew high-impedance staterate

XC3S200

XC3S400XC3S50XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000

7.718.38

8.879.63

nsns

Set/Reset TimesTIOSRHZ

Time from asserting TFF’s SR input to when LVCMOS25, 12mA

output drive, Fast slew the Output pin enters a high-impedance

ratestate

Time from asserting TFF’s SR input at TFF

to when the Output pin drives valid data

All

1.55

1.78

ns

TIOSRON(2)

XC3S200XC3S400XC3S50XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000

2.242.91

2.573.34

nsns

Notes:

1.2.3.

The numbers in this table are tested using the methodology presented in Table48 and are based on the operating conditions set forth inTable32 and Table35.

This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from Table47.For minimums, use the values reported by the Xilinx timing analyzer.

Table 47:Output Timing Adjustments for IOB

Add the Adjustment Below

Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the

Following Signal Standard (IOSTANDARD)

-5

Speed Grade

-4

Units

Single-Ended StandardsGTLGTL_DCIGTLPGTLP_DCIHSLVDCI_15HSLVDCI_18

00.130.030.231.510.81

0.020.150.040.271.740.94

nsnsnsnsnsns

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: DC and Switching Characteristics

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: DC and Switching Characteristics

DS099 (v3.1) June 27, 2013Product Specification

Spartan-3 FPGA Family: DC and Switching Characteristics

Table 50:Recommended Number of Simultaneously Switching Outputs per VCCO/GND Pair (Cont’d)

Signal Standard(IOSTANDARD)

LVDCI_15LVDCI_DV2_15HSLVDCI_15LVCMOS18

Slow

24681216

Fast

24681216

LVDCI_18LVDCI_DV2_18HSLVDCI_18LVCMOS25

Slow

2468121624

Fast

2468121624

LVDCI_25LVDCI_DV2_25HSLVDCI_25

Package

VQ100

6661913875513887557772813137665171087665777

TQ144

66613887551388755777161087665121087665777

PQ208

66613887551388755777121087665121087665777

CP132

666291999551913875577742191999652613137665777

FT256, FG320, FG456, FG676, FG900, FG1156

14141464342218131036211310961010107646332418117422015131185111111

DS099 (v3.1) June 27, 2013Product Specification