Boundary-Scan and JTAG Configuration
Introduction
Spartan?-6 devices support IEEE Std 1149.1, defining Test Access Port (TAP) and
boundary-scan architecture. These standards ensure the board-level integrity of individual components and the interconnections between them. In addition to connectivity testing, boundary-scan architecture offers flexibility for vendor-specific instructions, such as configure and verify, which add the capability of loading configuration data directly to FPGAs and compliant memories. TAP and boundary-scan architecture is commonly referred to collectively as JTAG.
Boundary-Scan for Spartan-6 Devices Using IEEE Std 1149.1
The Spartan-6 family is fully compliant with the IEEE Std 1149.1 (TAP and boundary-scan architecture). The architecture includes all mandatory elements defined in IEEE Std 1149.1. These elements include the TAP, the TAP controller, the Instruction register, the instruction decoder, the boundary-scan register, and the BYPASS register. The Spartan-6 family also supports a 32-bit Identification register in full compliance with the standard. Outlined in the following sections are the details of the JTAG architecture for Spartan-6 devices. More details about the JTAG architecture for Spartan-6devices can be found in Chapter10, Advanced JTAG Configurations.
Test Access Port (TAP)
The Spartan-6 FPGA TAP contains four mandatory dedicated pins as specified by the protocol in Spartan-6 devices and in typical JTAG architecture (see Figure10-1, page162). Three input pins and one output pin control the IEEE Std 1149.1 boundary-scan TAP controller. Optional control pins, such as Test Reset (TRST), and enable pins might be found on devices from other manufacturers. It is important to be aware of these optional signals when interfacing Xilinx devices with parts from different vendors because they might need to be driven.
The IEEE Std 1149.1 boundary-scan TAP controller is a state machine (16 states), shown in Chapter10, Advanced JTAG Configurations.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
STARTUP_SPARTAN6
STARTUP_SPARTAN6
The STARTUP_SPARTAN6 primitive provides a fabric interface to allow users to control some of global signals after configuration.
Table 4-3:STARTUP_SPARTAN6 Port Description
Signal Name EOSCLKGSR
TypeOutputInputInput
Function
Active-High. Absolute end of startup.User startup clock.
Active-High global set/reset signal. When this input is asserted, all flip-flops are restored to their initial value in the bitstream.
Clear the battery-backed RAM key when it is set. This signal needs to stay Low for 200ns (four clock cycles) to enable KEYCLEAR function.
Active-High global 3-state signal. When this input is asserted, all user I/Os are 3-stated.
Configuration internal oscillator clock output of approximately 50MHz that can be used as a generic clock source instead of a ring oscillator in the FPGA logic. If this port is not connected in the design, the oscillator is disabled.
Configuration logic main clock output. This signal outputs the clock associated with the current configuration mode. If the FPGA is in a Slave
configuration mode, the clock source is CCLK. If the FPGA is in a Master configuration mode, the clock source is the internal oscillator frequency (as defined by the BitGen option -g ConfigRate). Use the BitGen Persist option to maintain this signal after configuration.
KEYCLEARBInput
GTSCFGMCLK
InputOutput
CFGCLKOutput
DNA_PORT
The DNA_PORT provides access to a dedicated shift register, which can be loaded with the Device DNA data bits (unique ID) for a given Spartan?-6 device. In addition to shifting out the DNA data bits, this component allows for the inclusion of supplemental data bits for additional user data or allow for the DNA data to rollover (repeat DNA data after initial data has been shifted out). This component is primarily used in conjunction with other circuitry to build anti-cloning protection for the FPGA bitstream from possible theft.The DNA_PORT component must be instantiated to be used in a design. The instantiation template is found within the ISE? software. Project Navigator HDL templates. The instance declaration must be placed within the code. All inputs and outputs must be connected to the design to ensure proper operation.
To access the Device DNA data, the shift register must first be loaded by setting the
active-High READ signal for one clock cycle. After the shift register is loaded, the data can be synchronously shifted out by enabling the active-High SHIFT input and capturing the data from the DOUT output port. If desired, additional data can be appended to the end of the 57-bit shift register by connecting the appropriate logic to the DIN port. If DNA data
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
Configuration Data File Formats
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2024
Chapter 5:Configuration Details
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2024
Chapter 5:Configuration Details
Each logical bit of the FUSE_KEY and FUSE_CNTL registers consists of two eFUSE cells (primary and redundant), a flip-flop, and common logic elements for data multiplexing.
eFUSE Registers
A Spartan-6 FPGA has a total of three eFUSE registers. Table5-18 lists the eFUSE registers in Spartan-6 devices with their sizes and usage. The eFUSE bits are addressed so that the LSB is shifted in/out first and MSB is last.
Table 5-18:
eFUSE Registers
Size(Bits)256
[0:255]
(bit 255 shifted first)
Contents
Bitstream encryption key
Description
Stores key for use by AES bitstream decryptor. The eFUSE key can be used instead of the key stored in battery-backed SRAM. The AES key is used by the Spartan-6 FPGA decryption engine to load encrypted bitstreams. Depending on the read/write access bits in the CNTL register, the AES key can be programmed and read through the JTAG port.
Stores device DNA, a read-only register that is accessed through the JTAG port or the DNA_PORT primitive.Controls key use and read/write access to eFUSE registers. This register can be programmed and read through the JTAG port.
Register NameFUSE_KEY(1)
FUSE_ID57Device DNA[0:56]
(bit 56 shifted first)
FUSE_CNTL(1)
32Control BitsCNTL [31:0](bit 0 shifted first)
Notes:
1.FUSE_KEY and FUSE_CNTL are only available on 6SLX75/T, 6SLX100/T, and 6SLX150/T devices.
eFUSE Control Register (FUSE_CNTL)
This register contains six user programmable bits. These bits are used to select AES key usage and set the read/write protection for eFUSE registers, as detailed in Table5-19. Bit 0 is shifted in or out first.
The eFUSE bits are one-time programmable (OTP). Once programmed, they cannot be unprogrammed. For example, if access to a register is disabled, it cannot be re-enabled.Table 5-19:Bit #0:78
eFUSE CNTL Register BitsName--Description
Reserved
The user must program this bit after programming and verifying AES and CNTL registers to prevent any manipulation or readback of these registers.Reserved
Comments
CNTL SecurityDisable read and write of
the CNTL registers. Redundant with CNTL[12].
-Key Security
-
910
Disables read and write of The user must program this bit after KEY register. Redundant programming and verifying AES with CNTL[14].registers to prevent manipulation or
readback of these registers.-Reserved
11-
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UG380 (v2.11) March 22, 2024
FPGA可编程逻辑器件芯片XC2S50-5TQG144I中文规格书 - 图文
