Mode Registers
Mode registers (MR0–MR3) are used to define various modes of programmable opera-tions of the DDR3 SDRAM. A mode register is programmed via the mode register set(MRS) command during initialization, and it retains the stored information (except forMR0[8], which is self-clearing) until it is reprogrammed, RESET# goes LOW, the deviceloses power.
Contents of a mode register can be altered by re-executing the MRS command. Even ifthe user wants to modify only a subset of the mode register’s variables, all variablesmust be programmed when the MRS command is issued. Reprogramming the moderegister will not alter the contents of the memory array, provided it is performed cor-rectly.
The MRS command can only be issued (or re-issued) when all banks are idle and in theprecharged state (tRP is satisfied and no data bursts are in progress). After an MRS com-mand has been issued, two parameters must be satisfied: tMRD and tMOD. The control-ler must wait tMRD before initiating any subsequent MRS commands.
Figure 52: MRS to MRS Command Timing (tMRD)
CK#CK
Command
MRS1NOPNOPtMRDT0T1T2Ta0Ta1Ta2NOPNOPMRS2AddressValidValidCKE3
Indicates breakin time scale
Don’t Care
Notes:
1.Prior to issuing the MRS command, all banks must be idle and precharged, tRP (MIN)
must be satisfied, and no data bursts can be in progress.t2.MRD specifies the MRS to MRS command minimum cycle time.
3.CKE must be registered HIGH from the MRS command until tMRSPDEN (MIN) (see Pow-er-Down Mode (page 187)).
4.For a CAS latency change, tXPDLL timing must be met before any non-MRS command.
The controller must also wait tMOD before initiating any non-MRS commands (exclud-ing NOP and DES). The DRAM requires tMOD in order to update the requested features,with the exception of DLL RESET, which requires additional time. Until tMOD has beensatisfied, the updated features are to be assumed unavailable.
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Mode Register 0 (MR0)
Figure 53: MRS to nonMRS Command Timing (tMOD)
T0CK#CK
Command
MRSNOPNOPtMODT1T2Ta0Ta1Ta2NOPNOPnonMRSAddressValidValidCKE
Old settingValidNew settingUpdating settingIndicates breakin time scale
Don’t Care
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4Gb: x4, x8, x16 DDR3L SDRAMMode Register 0 (MR0)Figure 55: READ LatencyT0
CK#CKCommandREADNOPNOPNOPAL = 0, CL = 6DQS, DQS#DInDI n + 1DI n + 2DI n + 3DI n + 4NOPNOPNOPNOPNOPT1
T2
T3
T4
T5
T6
T7
T8
DQT0
CK#CKCommandREADT1T2T3T4T5T6T7T8
NOPNOPNOPNOPAL = 0, CL = 8NOPNOPNOPNOPDQS, DQS#DInDQTransitioning DataDon’t Care
Notes:
1.For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.2.Shown with nominal tDQSCK and nominal tDSDQ.
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Mode Register 1 (MR1)
Mode Register 1 (MR1)
The mode register 1 (MR1) controls additional functions and features not available inthe other mode registers: Q OFF (OUTPUT DISABLE), TDQS (for the x8 configurationonly), DLL ENABLE/DLL DISABLE, RTT,nom value (ODT), WRITE LEVELING, POSTEDCAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH. These functions are control-led via the bits shown in Figure 56 (page 146). The MR1 register is programmed via theMRS command and retains the stored information until it is reprogrammed, until RE-SET# goes LOW, or until the device loses power. Reprogramming the MR1 register willnot alter the contents of the memory array, provided it is performed correctly.
The MR1 register must be loaded when all banks are idle and no bursts are in progress.The controller must satisfy the specified timing parameters tMRD and tMOD before ini-tiating a subsequent operation.
Figure 56: Mode Register 1 (MR1) Definition
BA2BA1BA0A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0Address bus181716151413121110987650101010101Q OffTDQS01RTT01WLRTTODSM17 M16 00110101Mode Register Mode register set 0 (MR0)Mode register set 1 (MR1)Mode register set 2 (MR2)Mode register set 3 (MR3)M9M6M2000001011101110111M1201Q OffEnabledDisabledM1101TDQS DisabledEnabled43210RALTTODSDLLMode register 1 (MR1)M001DLL EnableEnable (normal)DisableM5M1Output Drive StrengthRTT,nom (ODT)3WritesRTT,nom disabledM7Write Levelization01Disable (normal)Enable00110101RZQ/6 (40? [NOM])RZQ/7 (34? [NOM])ReservedReservedRTT,nom (ODT)2Non-WritesRTT,nom disabledRZQ/4 (60? [NOM])RZQ/6 (40? [NOM])RZQ/8 (30? [NOM])ReservedReservedRZQ/4 (60? [NOM])RZQ/6 (40? [NOM])n/an/aReservedReservedM4M3Additive Latency (AL)00110101Disabled (AL = 0)AL = CL - 1AL = CL - 2Reserved010RZQ/2 (120? [NOM])RZQ/2 (120? [NOM])100RZQ/12 (20? [NOM])Notes:
1.MR1[18, 15:13, 10, 8] are reserved for future use and must be programmed to 0.
2.During write leveling, if MR1[7] and MR1[12] are 1, then all RTT,nom values are available
for use.
3.During write leveling, if MR1[7] is a 1, but MR1[12] is a 0, then only RTT,nom write values
are available for use.
DLL Enable/DLL Disable
The DLL may be enabled or disabled by programming MR1[0] during the LOAD MODEcommand, as shown in Figure 56 (page 146). The DLL must be enabled for normal oper-ation. DLL enable is required during power-up initialization and upon returning to nor-mal operation after having disabled the DLL for the purpose of debugging or evalua-tion. Enabling the DLL should always be followed by resetting the DLL using the appro-priate LOAD MODE command.
If the DLL is enabled prior to entering self refresh mode, the DLL is automatically disa-bled when entering SELF REFRESH operation and is automatically re-enabled and resetupon exit of SELF REFRESH operation. If the DLL is disabled prior to entering self re-09005aef85af8fa8
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Mode Register 1 (MR1)
fresh mode, the DLL remains disabled even upon exit of SELF REFRESH operation untilit is re-enabled and reset.
The DRAM is not tested to check—nor does Micron warrant compliance with—normalmode timings or functionality when the DLL is disabled. An attempt has been made tohave the DRAM operate in the normal mode where reasonably possible when the DLLhas been disabled; however, by industry standard, a few known exceptions are defined:?ODT is not allowed to be used
?The output data is no longer edge-aligned to the clock?CL and CWL can only be six clocks
When the DLL is disabled, timing and functionality can vary from the normal operationspecifications when the DLL is enabled (see DLL Disable Mode (page 125)). Disablingthe DLL also implies the need to change the clock frequency (see Input Clock Frequen-cy Change (page 129)).
Output Drive Strength
The DDR3 SDRAM uses a programmable impedance output buffer. The drive strengthmode register setting is defined by MR1[5, 1]. RZQ/7 (34? [NOM]) is the primary outputdriver impedance setting for DDR3 SDRAM devices. To calibrate the output driver im-pedance, an external precision resistor (RZQ) is connected between the ZQ ball andVSSQ. The value of the resistor must be 240? ±1%.
The output impedance is set during initialization. Additional impedance calibration up-dates do not affect device operation, and all data sheet timings and current specifica-tions are met during an update.
To meet the 34? specification, the output drive strength must be set to 34? during initi-alization. To obtain a calibrated output driver impedance after power-up, the DDR3SDRAM needs a calibration command that is part of the initialization and reset proce-dure.
OUTPUT ENABLE/DISABLE
The OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 56 (page146). When enabled (MR1[12] = 0), all outputs (DQ, DQS, DQS#) function when in thenormal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM outputs(DQ and DQS, DQS#) are tri-stated. The output disable feature is intended to be usedduring IDD characterization of the READ current and during tDQSS margining (writeleveling) only.
TDQS Enable
Termination data strobe (TDQS) is a feature of the x8 DDR3 SDRAM configuration thatprovides termination resistance (RTT) and may be useful in some system configurations.TDQS is not supported in x4 or x16 configurations. When enabled via the mode register(MR1[11]), the RTT that is applied to DQS and DQS# is also applied to TDQS and TDQS#.In contrast to the RDQS function of DDR2 SDRAM, DDR3’s TDQS provides the termina-tion resistance RTT only. The OUTPUT DATA STROBE function of RDQS is not providedby TDQS; thus, RON does not apply to TDQS and TDQS#. The TDQS and DM functionsshare the same ball. When the TDQS function is enabled via the mode register, the DMfunction is not supported. When the TDQS function is disabled, the DM function is pro-vided, and the TDQS# ball is not used. The TDQS function is available in the x8 DDR3
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MEMORY存储芯片ADM3075EARZ-REEL中文规格书 - 图文
