The StratixII clock networks can be disabled (powered down) by both static and dynamic approaches. When a clock net is powered down, all the logic fed by the clock net is in an off-state thereby reducing the overall power consumption of the device.
The global and regional clock networks can be powered down statically through a setting in the configuration (.sof or .pof) file. Clock networks that are not used are automatically powered down through configuration bit settings in the configuration file generated by the QuartusII software.The dynamic clock enable/disable feature allows the internal logic to control power up/down synchronously on GCLK and RCLK nets and PLL_OUT pins. This function is independent of the PLL and is applied directly on the clock network or PLL_OUT pin, as shown in Figures2–37 through 2–39.1
The following restrictions for the input clock pins apply:????
CLK0 pin -> inclk[0] of CLKCTRLCLK1 pin -> inclk[1] of CLKCTRLCLK2 pin -> inclk[0] of CLKCTRLCLK3 pin -> inclk[1] of CLKCTRL
In general, even CLK numbers connect to the inclk[0] port of CLKCTRL, and odd CLK numbers connect to the inclk[1] port of CLKCTRL.
Failure to comply with these restrictions will result in a no-fit error.
Enhanced & Fast PLLs
StratixII devices provide robust clock management and synthesis using up to four enhanced PLLs and eight fast PLLs. These PLLs increase performance and provide advanced clock interfacing and clock-frequency synthesis. With features such as clock switchover,
spread-spectrum clocking, reconfigurable bandwidth, phase control, and reconfigurable phase shifting, the StratixII device’s enhanced PLLs
provide you with complete control of clocks and system timing. The fast PLLs provide general purpose clocking with multiplication and phase shifting as well as high-speed outputs for high-speed differential I/O support. Enhanced and fast PLLs work together with the StratixII high-speed I/O and advanced clock architecture to provide significant improvements in system performance and bandwidth.
Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
Stratix II Device Handbook, Volume 1
StratixII Architecture
Table2–10 shows the enhanced PLL and fast PLL features in StratixII devices.
Table2–10.StratixII PLL Features
Feature
Clock multiplication and divisionPhase shiftClock switchoverPLL reconfigurationReconfigurable bandwidthSpread spectrum clockingProgrammable duty cycleNumber of internal clock outputsNumber of external clock outputsNumber of feedback clock inputsNotes to Table2–10:(1)(2)(3)(4)(5)(6)(7)(8)
For enhanced PLLs, m ranges from 1 to 256, while n and post-scale counters range from 1 to 512 with 50% duty cycle.
For fast PLLs, m, and post-scale counters range from 1 to 32. The n counter ranges from 1 to 4.
The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8.
For degree increments, StratixII devices can shift all output frequencies in increments of at least 45. Smaller degree increments are possible depending on the frequency and divide parameters.StratixII fast PLLs only support manual clock switchover.
Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a datachannel to generate txclkout.
If the feedback input is used, you lose one (or two, if FBIN is differential) external clock output pin.
Every StratixII device has at least two enhanced PLLs with one single-ended or differential external feedback input per PLL.
Enhanced PLL
m/(n × post-scale counter) (1)Down to 125-ps increments (3), (4)
Fast PLL
m/(n × post-scale counter) (2)Down to 125-ps increments (3), (4)
vvvvv
6
Threedifferential/sixsingle-endedOne single-ended or differential
(7), (8)
v (5)vvv
4(6)
Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
Figure2–40 shows a top-level diagram of the StratixII device and PLL floorplan.
Figure2–40.PLL Locations
CLK[15..12]11FPLL7CLK7510FPLL10CLKCLK[3..0]1243CLK[8..11]PLLsFPLL8CLK89FPLL9CLK126CLK[7..4]Figures2–41 and 2–42 shows the global and regional clocking from the fast PLL outputs and the side clock pins.
Stratix II Device Handbook, Volume 1
StratixII Architecture
Figure2–41.Global & Regional Clock Connections from Center Clock Pins & Fast PLL OutputsNote(1)
CLK11CLK10CLK9C3C0C1C2FastPLL 3C3CLK8C0C1C2FastPLL 4RCK23RCK21RCK19RCK17GCK11GCK9Logc ArraySgna InputTo CockNetworkGCK2GCK0RCK6RCK4RCK2C0C1C2C3C0C1C2FastPLL 1CLK0CLK1CLK2FastPLL 2Notes to Figure2–41:(1)
EP2S15 and EP2S30 devices only have four fast PLLs (1, 2, 3, and 4), but the connectivity from these four PLLs to the global and regional clock networks remains the same as shown.
The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input.The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
(2)
Stratix II Device Handbook, Volume 1
CLK3C3RCK0RCK1RCK3RCK5RCK7GCK1GCK3GCK8GCK10RCK16RCK18RCK20RCK22
FPGA可编程逻辑器件芯片EP1S25F780C7中文规格书 - 图文
