SIII51014-1.5
Introduction
This chapter provides an overview of the design security feature and its
implementation on Stratix?III devices using advanced encryption standard (AES) as well as security modes available in StratixIII devices.
As StratixIII devices start to play a role in larger and more critical designs in
competitive commercial and military environments, it is increasingly important to protect the designs from copying, reverse engineering, and tampering. StratixIII devices address these concerns and are the industry’s only high-density,
high-performance devices with both volatile and non-volatile security feature
support. StratixIII devices have the ability to decrypt configuration bitstreams using the AES algorithm, an industry standard encryption algorithm that is FIPS-197
certified. They also have a design security feature that utilizes a 256-bit security key.Altera? StratixIII devices store configuration data in static random access memory (SRAM) configuration cells during device operation. Because SRAM memory is volatile, SRAM cells must be loaded with configuration data each time the device powers-up. It is possible to intercept configuration data when it is being transmitted from the memory source (flash memory or a configuration device) to the device. The intercepted configuration data could then be used to configure another device.When using the StratixIII design security feature, the security key is stored in the StratixIII device. Depending on the security mode, you can configure the StratixIII device using a configuration file that is encrypted with the same key, or for board testing, configured with a normal configuration file.
The design security feature is available when configuring StratixIII devices using the fast passive parallel (FPP) configuration mode with an external host (such as a MAX?II device or microprocessor), or when using fast active serial (AS) or passive serial (PS) configuration schemes. However, the design security feature is also available in remote update with fast AS configuration mode. The design security feature is not available when you are configuring your StratixIII device using Joint Test Action Group (JTAG)-based configuration. For more information, refer to “Supported Configuration Schemes” on page14–5.
StratixIII Security Protection
StratixIII device designs are protected from copying, reverse engineering, and tampering using configuration bitstream encryption.
Security Against Copying
The security key is securely stored in the StratixIII device and cannot be read out through any interfaces. In addition, as configuration file read-back is not supported in StratixIII devices, the design information cannot be copied.
Stratix III Device Handbook, Volume 1
Chapter 1:StratixIII Device Datasheet: DC and Switching CharacteristicsElectrical Characteristics
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Datasheet: DC and Switching Characteristics
Electrical Characteristics
Table1–6.Bus Hold Parameters for StratixIII Devices(Part 2 of 2)
VCCIO
ParameterSymbolConditions1.2VMin
Max
-120
1.5VMin
—
1.8VMin
—
2.5VMin
—
3.0V/3.3VMin
—
Unit
Max
-160
Max
-200
Max
-300
Max
-500
μA
High overdrive currentBus-hold trip point
IODHVTRIP
0V — — 0.45 0.95 0.50 1.00 0.68 1.07 0.70 1.70 0.80 2.00 V On-Chip Termination (OCT) Specifications If you enable OCT calibration, calibration is automatically performed at power-up for the I/Os connected to the calibration block. Table1–7 lists the StratixIII OCT calibration block accuracy specifications. Table1–7.On-Chip Termination Calibration Accuracy Specifications for StratixIII Devices(Note1) Calibration Accuracy Symbol Description Conditions C2 25-? RS (2) 3.3, 3.0, 2.5, 1.8, 1.5, 1.250-? RS 3.3, 3.0, 2.5, 1.8, 1.5, 1.250-? RT 2.5, 1.8, 1.5, 1.220-??RS to 60-??RS 3.3, 3.0, 2.5, 1.8, 1.5, 1.2 Internal series termination with calibration (25-? setting)Internal series termination with calibration (50-? setting) VCCIO = 3.3, 3.0, 2.5, 1.8, 1.5, 1.2VVCCIO = 3.3, 3.0, 2.5, 1.8, 1.5, 1.2V ±8±8±10 C3, I3±8±8±10 C4, I4±8±8±10 %%%Unit Internal parallel termination with VCCIO = 2.5, 1.8, 1.5, 1.2V calibration (50-? setting)Expanded range for internal series termination with calibration (Between 20-? to 60-??setting)Internal left shift series termination with calibration (25-? RS _left_shift setting)Internal series termination with calibration VCCIO = 3.3, 3.0, 2.5, 1.8, 1.5, 1.2V (3) VCCIO = 3.3, 3.0, 2.5, 1.8, 1.5, 1.2V (4) ±10±10±10% 25-? RS _left_shift ROCT_CAL Notes to Table1–7: ±10±10±10% (1)OCT calibration accuracy is valid at the time of calibration only.(2)25-? RS not supported for 1.5V and 1.2V in Row I/O.(3)1.5V and 1.2V only supports 40-? to 60-? expanded range. (4)For resistance tolerance after power-up calibration, refer to Equation1–1 and Table1–9 on page1–8. Stratix III Device Handbook, Volume 2 Chapter 1:StratixIII Device Datasheet: DC and Switching CharacteristicsElectrical Characteristics The accuracy listed in Table1–7 is valid at the time of calibration. If the voltage or temperature changes, the termination resistance value varies. Table1–8 lists the resistance tolerance for StratixIII OCT. Table1–8.On-Chip Termination Resistance Tolerance Specification for StratixIII Devices Symbol ROCT_UNCAL 25-? RS 3.3, 3.0, 2.525-? RS 1.8, 1.525-? RS 1.250-? RS 3.3, 3.0, 2.550-? RS 1.8, 1.550-? RS 1.2RD Description Internal series termination without calibration Internal series termination without calibration (25-? setting)Internal series termination without calibration (25-? setting)Internal series termination without calibration (25-? setting)Internal series termination without calibration (50-? setting)Internal series termination without calibration (50-? setting)Internal series termination without calibration (50-? setting)Internal differential termination for LVDS technology (100-??setting) VCCIO = 3.3, 3.0, 2.5VVCCIO = 1.8, 1.5VVCCIO = 1.2VVCCIO = 3.3, 3.0, 2.5VVCCIO = 1.8, 1.5VVCCIO = 1.2VVCCIO = 2.5V Conditions Resistance ToleranceC2—±30±30±35±30±30±35 ±40±50±60±40±50±60-15 to 35 ±40±50±60±40±50±60 %%%%%%% C3, I3 C4, I4 Unit Table1–9 lists OCT variation with temperature and voltage after power-up calibration. Use Table1–9 and Equation1–1 to determine OCT variation without re-calibration. Equation1–1.OCT Variation Without Re-Calibration(Note1) dRdR ROCT=RSCAL?1+?------??T???------??V?? ??dVdT Notes to Equation1–1: (1)ROCT value calculated from Equation1–1 shows the range of OCT resistance with the variation of temperature and VCCIO.(2)RSCAL is the OCT resistance value at power-up. (3)?T is the variation of temperature with respect to the temperature at power-up.(4)?V is the variation of voltage with respect to the VCCIO at power-up.(5)dR/dT is the percentage change of RSCAL with temperature.(6)dR/dV is the percentage change of RSCAL with voltage. Stratix III Device Handbook, Volume 2 Chapter 1:StratixIII Device Datasheet: DC and Switching Characteristics Electrical Characteristics Table1–18.Differential I/O Standard Specifications (Part 2 of 2)I/O Standard VCCIO (V)Min2.3752.3752.3752.3752.3752.375 Typ2.52.52.52.52.52.5 Max2.6252.6252.6252.6252.625 Min0.10.10.10.10.2 VID (V) (1)Condition VCM = 1.25VCM = 1.25VCM = 1.25VCM = 1.25 VICM(DC) (V) Max————0.60.6—— Min0.05 (6) 1.05 VOD (V) (2) Max 1.8 VOCM (V) (2) Max0.60.60.60.60.60.6—— Min1.01.00.50.50.50.5—— Typ1.251.251.21.21.21.2—— Max1.51.51.41.51.41.5—— ConditionDmax?? 700 Mbps Min0.2470.2470.10.10.250.25—— Typ——0.20.2———— 2.5V LVDS (Column I/O)RSDS (Row I/O)RSDS (Column I/O)Mini-LVDS (Row I/O)Mini-LVDS (Column I/0)LVPECL(3) (6)1.55 (6)1.41.41.3251.3251.8 (4)1.6(4) Dmax >700 Mbps (6)0.30.30.40.40.61.0 ————Dmax?? 700 Mbps ———— 2.625 0.20.30.3 2.375 2.5 2.625(5)(5)(5)2.375(5) 2.5(5) 2.625(5) Dmax >700 Mbps Notes to Table1–18: (1)The minimum VID value is applicable over the entire common mode range, VCM.(2)RL range: 90 ??RL ? 110?. (3)Column and row I/O banks support LVPECL I/O standards for input operation only on dedicated clock input pins. Differential clock inputs in column I/O use VCC_CLKIN that must be powered by 2.5 V. Differential clock inputs in row I/O banks are powered by VCCPD.(4)The receiver voltage input range for the data rate when Dmax > 700Mbps is 0.85V ??VIN ??1.75V. The receiver voltage input range for the data rate when Dmax ??700Mbps is 0.45V ??VIN ??1.95V.(5)Power supply for the column I/O LVPECL differential clock input buffer is VCC_CLKIN. (6)The receiver voltage input range for the data rate when Dmax > 700Mbps is 1.0V ??VIN ??1.6V. The receiver voltage input range for the data rate when Dmax ??700Mbps is zeroV ??VIN ??1.85V. Power Consumption Altera offers two ways to estimate power for a design: the Excel-based Early Power Estimator (EPE) and the Quartus?II PowerPlay Power Analyzer feature. The interactive Excel-based Early Power Estimator is typically used prior to designing the FPGA in order to get a magnitude estimate of the device power. The QuartusII PowerPlay Power Analyzer provides estimation based on the specifics of the design after place-and-route is complete. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities which, when combined with detailed circuit models, can yield very accurate power estimation. Refer to Table1–4 on page1–5 for supply current estimates for VCCPGM and VCC_CLKIN. Use the EPE and PowerPlay Power Analyzer for current estimates of remaining power supplies. f For more information about power estimation tools, refer to the PowerPlay Early Power Estimator User Guide For StratixIII FPGAs and the PowerPlay Power Analysis chapter in the QuartusII Handbook. Stratix III Device Handbook, Volume 2
FPGA可编程逻辑器件芯片EP1S30B1020C6N中文规格书 - 图文
