The DLL component has two clock inputs, CLKIN and CLKFB, as well as seven clock outputs, CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as described in Table16. The clock outputs drive simultaneously; however, the High Frequency mode only supports a subset of the outputs available in the Low Frequency mode. See DLL Frequency Modes, page35. Signals that initialize and report the state of the DLL are discussed in The Status Logic Component, page41.
Table 16:DLL Signals
Mode Support
SignalCLKINCLKFBCLK0CLK90CLK180CLK270CLK2XCLK2X180CLKDV
DirectionInputInputOutputOutputOutputOutputOutputOutputOutput
Accepts original clock signal.
Description
Low Frequency
YesYesYesYesYesYesYesYesYes
High Frequency
YesYesYesNoYesNoNoNoYes
Accepts either CLK0 or CLK2X as feed back signal. (Set CLK_FEEDBACK attribute accordingly).
Generates clock signal with same frequency and phase as CLKIN.
Generates clock signal with same frequency as CLKIN, only phase-shifted 90°.Generates clock signal with same frequency as CLKIN, only phase-shifted 180°.Generates clock signal with same frequency as CLKIN, only phase-shifted 270°.Generates clock signal with same phase as CLKIN, only twice the frequency.Generates clock signal with twice the frequency of CLKIN, phase-shifted 180° with respect to CLKIN.
Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower frequency clock signal that is phase-aligned to CLKIN.
The clock signal supplied to the CLKIN input serves as a reference waveform, with which the DLL seeks to align the
feedback signal at the CLKFB input. When eliminating clock skew, the common approach to using the DLL is as follows: The CLK0 signal is passed through the clock distribution network to all the registers it synchronizes. These registers are either internal or external to the FPGA. After passing through the clock distribution network, the clock signal returns to the DLL via a feedback line called CLKFB. The control block inside the DLL measures the phase error between CLKFB and CLKIN. This phase error is a measure of the clock skew that the clock distribution network introduces. The control block activates the appropriate number of delay elements to cancel out the clock skew. Once the DLL has brought the CLK0 signal in phase with the CLKIN signal, it asserts the LOCKED output, indicating a “lock” on to the CLKIN signal.
DLL Attributes and Related Functions
A number of different functional options can be set for the DLL component through the use of the attributes described in Table17. Each attribute is described in detail in the sections that follow:Table 17:DLL Attributes
Attribute
CLK_FEEDBACK
DLL_FREQUENCY_MODE CLKIN_DIVIDE_BY_2CLKDV_DIVIDE
Description
Chooses between High Frequency and Low Frequency modesHalves the frequency of the CLKIN signal just as it enters the DCM Selects constant used to divide the CLKIN input frequency to generate the CLKDV output frequency
Enables 50% duty cycle correction for the CLK0, CLK90, CLK180, and CLK270 outputs
Values
LOW, HIGH TRUE, FALSE
1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0, 6.5, 7.0, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16.TRUE, FALSE
Chooses either the CLK0 or CLK2X output to drive the CLKFB inputNONE, 1X, 2X
DUTY_CYCLE_CORRECTION
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 23a.CLKOUT_PHASE_SHIFT = NONECLKINCLKFBb.CLKOUT_PHASE_SHIFT = FIXEDCLKINShift Range over all P Values:–2550P256* TCLKIN+255CLKFBc.CLKOUT_PHASE_SHIFT = VARIABLECLKINShift Range over all P Values:–2550P* TCLKIN256+255CLKFB beforeDecrementShift Range over all N Values:CLKFB afterDecrement–255N* T256CLKIN0+255DS099-2_11_031303Notes: 1.2.
P represents the integer value ranging from –255 to +255 to which the PHASE_SHIFT attribute is assigned.
N is an integer value ranging from –255 to +255 that represents the net phase shift effect from a series of incrementand/or decrement operations.
N = {Total number of increments} – {Total number of decrements}
A positive value for N indicates a net increment; a negative value indicates a net decrement.
Figure 23:Phase Shifter Waveforms
The Status Logic Component
The Status Logic component not only reports on the state of the DCM but also provides a means of resetting the DCM to an initial known state. The signals associated with the Status Logic component are described in Table22.
As a rule, the Reset (RST) input is asserted only upon configuring the device or changing the CLKIN frequency. A DCM reset does not affect attribute values (e.g., CLKFX_MULTIPLY and CLKFX_DIVIDE). If not used, RST must be tied to GND.The eight bits of the STATUS bus are defined in Table23.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
X-Ref Target - Figure 29Power-OnSet PROG_B Lowafter Power-OnVCCINT >1Vand VCCAUX > 2Vand VCCO Bank 4 > 1VNoYesClear configuration memoryYesPROG_B = LowNoNoINIT_B = High?YesSample mode pinsLoad configurationdata framesCRCcorrect?NoINIT_B goes Low.Abort Start-UpYesStart-UpsequenceUser modeNoReconfigure?YesDS099_26_041103Figure 29:Configuration Flow Diagram for the Serial and Parallel Modes
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XC2S384-10FT256C中文规格书 - 图文
