Dynamic Reconfiguration of Functional Blocks
is presented simultaneously with the write address and DWE and DEN signals prior to the next positive edge of DCLK. The port asserts DRDY for one clock cycle when it is ready to accept more data. The timing requirements relative to DCLK for all the other signals are the same. The output data is not registered in the functional blocks. Output (read) data is available after some cycles following the cycle that DEN and DADDR are asserted. The availability of output data is indicated by the assertion of DRDY.
Figure5-4 and Figure5-5 show the timing relationships between the port signals for write and read operations. Absolute timing parameters, such as maximum DCLK frequency, setup time, etc., are defined in DS202, Virtex-5 Data Sheet: DC and Switching Characteristics.
DCLKDENDRDYDWE
DADDR[m:0]
DI[n:0]DO[n:0]
UG191_c5_04_050406
bbBB
Figure 5-4:Write Timing with Wait States
DCLKDENDRDYDWE
DADDR[m:0]
DI[n:0]DO[n:0]
AA
UG191_c5_05_050406
AA
Figure 5-5:Read Timing with Wait States
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
Chapter 5:Dynamic Reconfiguration Port (DRP)
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
Configuration Registers
Watchdog Timer Register (TIMER)
The Watchdog timer is automatically disabled for fallback bitstreams. The name of each bit position in the TIMER register is given in Figure6-7 and described in Table6-13.ReservedTIMER_CFG_MONTIMER_USR_MONTIMER_VALUEDescription
Bit IndexValue
310
300
290
280
270
260
250
240
230
220
210
200
190
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
00
Figure 6-7:TIMER Register
Table 6-13:
TIMER Register DescriptionName
TIMER_USR_MON
Bit Index
25
Description
Watchdog is enabled during user mode:0: Disabled1: Enabled
Watchdog is enabled during configuration:0: Disabled1: Enabled
Watchdog time-out value, CFG_MCLK is used for this counter. CFG_MCLK is about 50MHz by default, and is pre-divided by 256.
TIMER_CFG_MON24
TIMER_VALUE[23:0]
Boot History Status Register (BOOTSTS)
This register can only be reset by POR, asserting PROGRAM_B, or issuing a JPROGRAM instruction. At EOS or an error condition, status (_0) is shifted to status (_1), and status (_0) is updated with the current status. The name of each bit position in the BOOTSTS register is given in Figure6-8 and described in Table6-14.
ReservedVALID_0FALLBACK_0IPROG_0WTO_ERROR_0ID_ERROR_0CRC_ERROR_0WRAP_ERROR_0RBCRC_ERROR_0VALID_1FALLBACK_1IPROG_1WTO_ERROR_1ID_ERROR_1CRC_ERROR_1WRAP_ERROR_1RBCRC_ERROR_1Description
Bit IndexValue
310
300
290
280
270
260
250
240
230
220
210
200
190
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
00
Figure 6-8:BOOTSTS Register
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
FPGA可编程逻辑器件芯片XC2V6000-5BG575C中文规格书
