Two saturation modes are supported in ArriaII devices:
■■
Asymmetric saturation modeSymmetric saturation mode
You must select one of the two options at compile time.
In 2’s complement format, the maximum negative number that can be represented is –2 (n-1), and the maximum positive number is 2(n-1) – 1. Symmetrical saturation limitsthe maximum negative number to –2(n-1) + 1. For example, for 32 bits:
■■
Asymmetric 32-bit saturation: Max = 0×7FFFFFFF, Min = 0×80000000Symmetric 32-bit saturation: Max = 0×7FFFFFFF, Min = 0×80000001
Table4–8 lists how the saturation works. In this example, a 44-bit input is saturated to 36-bits.
Table4–8.Examples of Saturation
44 to 36 Bits Saturation
5926AC01342hADA38D2210h
Symmetric SAT Result
7FFFFFFFFh800000001h
Asymmetric SAT Result
7FFFFFFFFh800000000h
ArriaII devices have up to 16 configurable bit positions out of the 44-bit bus ([43:0]) for the rounding and saturate logic unit, providing higher flexibility. You must select the 16 configurable bit positions at compile time. These 16-bit positions are located at bits [21:6] for rounding and [43:28] for saturation, as shown in Figure4–20.
Figure4–20.Rounding and Saturation Locations
16 User defined SAT Positions (bit 43-28)434229281016 User defined RND Positions (bit 21-6)434221207601
For symmetric saturation, the RND bit position is to determine where the LSP for the saturated data is located.
You can use the rounding and saturation function as described in regular supported multiplication operations shown in Table4–2 on page4–7. However, for accumulation type operations, the following convention is used.
The functionality of the rounding logic unit is in the format of:
Result = RND[∑(A × B)], when used for an accumulation type of operation.Likewise, the functionality of the saturation logic unit is in the format of:Result = SAT[∑(A × B)], when used for an accumulation type of operation.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 4:DSP Blocks in ArriaII Devices
Arria II Operational Mode Descriptions
If both the rounding and saturation logic units are used for an accumulation type of operation, the format is: Result = SAT[RND[∑(A × B)]]
DSP Block Control Signals
You can configure the ArriaII DSP block with a set of static and dynamic signals. At run time, you can configure the DSP block dynamic signals to toggle or not. Table4–9 shows a list of dynamic signals for the DSP block. Table4–9 lists the DSP block dynamic signals.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 4:DSP Blocks in ArriaII DevicesSoftware Support for ArriaII Devices
Table4–9.DSP Block Dynamic Signals for DSP Block in Arria II Devices(Part 2 of 2)
Signal Name
shift_rightFunction
shift_right = 1, shift right feature is enabled
Count1
DSP Block Dynamic Signals per Full-DSP Blockclock0clock1clock2clock3ena0ena1ena2ena3aclr0aclr1aclr2aclr3Total Count per Half- and Full-DSP Blocks
33
DSP block-wide asynchronous clear signals (active low)
4
Input and Pipeline Register enable signals
4
DSP-block-wide clock signals
4
Software Support for ArriaII Devices
Altera provides two distinct methods for implementing various modes of the DSP block in a design: instantiation and inference. Both methods use the following QuartusII megafunctions:
■■■■
LPM_MULTALTMULT_ADDALTMULT_ACCUMALTFP_MULT
You can instantiate the megafunctions in the QuartusII software to use the DSP block. Alternatively, with inference, you can create an HDL design and synthesize it with a third-party synthesis tool (such as LeonardoSpectrum, Synplify, or QuartusII Native Synthesis) that infers the appropriate megafunction by recognizing multipliers,
multiplier adders, multiplier accumulators, and shift functions. With either method, the QuartusII software maps the functionality to the DSP blocks during compilation.
fFor instructions about using the megafunctions and the MegaWizard Plug-In
Manager, refer to the QuartusII Software Help.fFor more information, refer to Section III: Synthesis in volume 1 of the QuartusII
Handbook.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 4:DSP Blocks in ArriaII Devices
Document Revision History
Document Revision History
Table4–10 shows the revision history for this document.
Table4–10.Document Revision History
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 5:Clock Networks and PLLs in Arria II DevicesClock Networks in ArriaII Devices
Clock Resources
4
GCLK[0..3] (1)GCLK[4..7]GCLK[8..11]GCLK[12..15]—v——
5—v——
6—v——
7—v——
8——v—
CLK (p/n Pins)9——v—
10——v—
11——v—
12———v
13———v
14———v
15———v
CLK (p/n Pins)
Clock Resources
0
GCLK[0..3]GCLK[4..7]v—
1v—
2v—
3v—
4—v
5—v
6—v
7—v
8——
9——
10——
11——
12——
13——
14——
15——
Arria II Device Handbook Volume 1: Device Interfaces and Integration
FPGA可编程逻辑器件芯片EP2AGX190FF35C6N中文规格书 - 图文
