Spartan-3 FPGA Family
Data Sheet
DS099 June 27, 2013
Product Specification
Module 1:
Introduction and Ordering Information
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IntroductionFeatures
Architectural OverviewArray Sizes and ResourcesUser I/O ChartOrdering Information
Module 4: Pinout Descriptions
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Pin Descriptions?
Pin Behavior During ConfigurationPackage OverviewPinout Tables?
Footprints
Module 2: Functional Description
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Input/Output Blocks (IOBs)?????
IOB Overview
SelectIO? Interface I/O Standards
Configurable Logic Blocks (CLBs)Block RAMDedicated Multipliers
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Digital Clock Manager (DCM)Clock NetworkConfiguration
Module 3:
DC and Switching Characteristics
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DC Electrical Characteristics?????
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Absolute Maximum RatingsSupply Voltage SpecificationsRecommended Operating ConditionsDC CharacteristicsI/O Timing
Internal Logic TimingDCM Timing
Configuration and JTAG Timing
Switching Characteristics
DS099 June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
IOBs
For additional information, refer to the chapter entitled “Using I/O Resources” in UG331: Spartan-3 Generation FPGA User Guide.
IOB Overview
The Input/Output Block (IOB) provides a programmable, bidirectional interface between an I/O pin and the FPGA’s internal logic.
A simplified diagram of the IOB’s internal structure appears in Figure7. There are three main signal paths within the IOB: the output path, input path, and 3-state path. Each path has its own pair of storage elements that can act as either registers or latches. For more information, see the Storage Element Functions section. The three main signal paths are as follows:?
The input path carries data from the pad, which is bonded to a package pin, through an optional programmable delayelement directly to the I line. There are alternate routes through a pair of storage elements to the IQ1 and IQ2 lines.The IOB outputs I, IQ1, and IQ2 all lead to the FPGA’s internal logic. The delay element can be set to ensure a holdtime of zero.
The output path, starting with the O1 and O2 lines, carries data from the FPGA’s internal logic through a multiplexerand then a three-state driver to the IOB pad. In addition to this direct path, the multiplexer provides the option to inserta pair of storage elements.
The 3-state path determines when the output driver is high impedance. The T1 and T2 lines carry data from the
FPGA’s internal logic through a multiplexer to the output driver. In addition to this direct path, the multiplexer providesthe option to insert a pair of storage elements. When the T1 or T2 lines are asserted High, the output driver ishigh-impedance (floating, hi-Z). The output driver is active-Low enabled.
All signal paths entering the IOB, including those associated with the storage elements, have an inverter option. Anyinverter placed on these paths is automatically absorbed into the IOB.
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Storage Element Functions
There are three pairs of storage elements in each IOB, one pair for each of the three paths. It is possible to configure each of these storage elements as an edge-triggered D-type flip-flop (FD) or a level-sensitive latch (LD).
The storage-element-pair on either the Output path or the Three-State path can be used together with a special multiplexer to produce Double-Data-Rate (DDR) transmission. This is accomplished by taking data synchronized to the clock signal’s rising edge and converting them to bits synchronized on both the rising and the falling edge. The combination of two registers and a multiplexer is referred to as a Double-Data-Rate D-type flip-flop (FDDR). See Double-Data-Rate Transmission, page12 for more information.
The signal paths associated with the storage element are described in Table5.Table 5:Storage Element Signal Description
Storage Element SignalDQCKCESRREV
DescriptionData inputData outputClock inputClock Enable inputSet/ResetReverse
Function
Data at this input is stored on the active edge of CK enabled by CE. For latch operation when the input is enabled, data passes directly to the output Q.
The data on this output reflects the state of the storage element. For operation as a latch in transparent mode, Q will mirror the data at D.
A signal’s active edge on this input with CE asserted, loads data into the storage element. When asserted, this input enables CK. If not connected, CE defaults to the asserted state. Forces storage element into the state specified by the SRHIGH/SRLOW attributes. The
SYNC/ASYNC attribute setting determines if the SR input is synchronized to the clock or not.Used together with SR. Forces storage element into the state opposite from what SR does.
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Functional Description
Configuration is automatically initiated after power-on unless it is delayed by the user. INIT_B is an open-drain line that the FPGA holds Low during the clearing of the configuration memory. Extending the time that the pin is Low causes the configuration sequencer to wait. Thus, configuration is delayed by preventing entry into the phase where data is loaded.The configuration process can also be initiated by asserting the PROG_B pin. The end of the memory-clearing phase is signaled by the INIT_B pin going High. At this point, the configuration data is written to the FPGA. The FPGA pulses the Global Set/Reset (GSR) signal at the end of configuration, resetting all flip-flops. The completion of the entire process is signaled by the DONE pin going High.
X-Ref Target - Figure 31DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 46:Timing for the IOB Three-State Path
Speed Grade
Symbol
Description
Conditions
Device
-5Max(3)
Synchronous Output Enable/Disable TimesTIOCKHZ
Time from the active transition at the OTCLK input of the Three-state Flip-Flop (TFF) to when the Output pin enters the high-impedance state
Time from the active transition at TFF’s OTCLK input to when the Output pin drives valid data
LVCMOS25, 12mA output drive, Fast slew rate
All
0.74
0.85
ns
-4Max(3)
Units
TIOCKON(2)
All0.720.82ns
Asynchronous Output Enable/Disable TimesTGTS
Time from asserting the Global Three State LVCMOS25, 12mA (GTS) net to when the Output pin enters the output drive, Fast slew high-impedance staterate
XC3S200
XC3S400XC3S50XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
7.718.38
8.879.63
nsns
Set/Reset TimesTIOSRHZ
Time from asserting TFF’s SR input to when LVCMOS25, 12mA
output drive, Fast slew the Output pin enters a high-impedance
ratestate
Time from asserting TFF’s SR input at TFF
to when the Output pin drives valid data
All
1.55
1.78
ns
TIOSRON(2)
XC3S200XC3S400XC3S50XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000
2.242.91
2.573.34
nsns
Notes:
1.2.3.
The numbers in this table are tested using the methodology presented in Table48 and are based on the operating conditions set forth inTable32 and Table35.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. When this is true, add the appropriate Output adjustment from Table47.For minimums, use the values reported by the Xilinx timing analyzer.
Table 47:Output Timing Adjustments for IOB
Add the Adjustment Below
Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the
Following Signal Standard (IOSTANDARD)
-5
Speed Grade
-4
Units
Single-Ended StandardsGTLGTL_DCIGTLPGTLP_DCIHSLVDCI_15HSLVDCI_18
00.130.030.231.510.81
0.020.150.040.271.740.94
nsnsnsnsnsns
DS099 (v3.1) June 27, 2013Product Specification
FPGA可编程逻辑器件芯片XC2S150-5FG256I中文规格书 - 图文
