Zynq-7000SoC
(Z-7030, Z-7035, Z-7045, and Z-7100):DC and AC Switching Characteristics
DS191 (v1.18.1) July 2, 2018
Product Specification
Introduction
The Zynq?-7000 SoCs are available in -3, -2, -2LI, -1, and -1LQ speed grades, with -3 having the highest performance. The -2LI devices operate at programmable logic (PL)VCCINT/VCCBRAM=0.95V and are screened for lower maximum static power. The speed specification of a -2LI device is the same as that of a -2device. The -1LQ devices operate at the same voltage and speed as the -1Q devices and are screened for lower power. Zynq-7000 device DC and AC characteristics are specified in commercial,
extended, industrial, and expanded (Q-temp) temperature ranges. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). However, only selected speed grades and/or devices are available in the commercial, extended, or industrial temperature ranges.
All supply voltage and junction temperature specifications are representative of worst-case conditions. The
parameters included are common to popular designs and typical applications.
The available device/package combinations are outlined in:???
Zynq-7000SoC Overview (DS190)
Defense-grade Zynq-7000QSoC Overview (DS196)XAZynq-7000SoC Overview (DS188)
This Zynq-7000 SoC data sheet, which covers the specifications for the XC7Z030, XA7Z030, XQ7Z030, XC7Z035, XC7Z045, XQ7Z045, XC7Z100, and XQ7Z100 complements the Zynq-7000 SoC documentation suite available on the Xilinx website.
DC Characteristics
Table 1:Absolute Maximum Ratings(1)
Symbol
Processing System (PS)VCCPINTVCCPAUXVCCPLLVCCO_DDRVCCO_MIO(2)VPREFVPIN(2)(3)(4)(5)
PS internal logic supply voltagePS auxiliary supply voltagePS PLL supplyPS DDR I/O supplyPS MIO I/O supplyPS input reference voltagePS MIO I/O input voltagePS DDR I/O input voltage
–0.5–0.5–0.5–0.5–0.5–0.5–0.40–0.55
1.12.02.02.03.62.0
VCCO_MIO+0.55VCCO_DDR+0.55
1.11.12.03.62.02.06
VVVVVVVV
DescriptionMinMaxUnits
Programmable Logic (PL)VCCINTVCCBRAMVCCAUXVCCO
VCCAUX_IO(4)
PL internal supply voltage
PL supply voltage for the block RAM memoriesPL auxiliary supply voltage
PL output drivers supply voltage for HR I/O banksPL output drivers supply voltage for HP I/O banksAuxiliary supply voltage
–0.5–0.5–0.5–0.5–0.5–0.5
VVVVVV
DS191 (v1.18.1) July 2, 2018Product Specification
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
DS191 (v1.18.1) July 2, 2018Product Specification
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
Table 4:VIN Maximum Allowed AC Voltage Overshoot and Undershoot for PS I/O and PL HR I/O Banks(1)(2)
AC Voltage Overshoot
% of UI @–40°C to 125°C
AC Voltage Undershoot
–0.40
VCCO+0.55
100
–0.45–0.50–0.55
VCCO+0.60VCCO+0.65VCCO+0.70VCCO+0.75VCCO+0.80VCCO+0.85VCCO+0.90VCCO+0.95
46.621.29.754.552.151.020.490.24
–0.60–0.65–0.70–0.75–0.80–0.85–0.90–0.95
% of UI @–40°C to 125°C
10061.725.811.04.772.100.940.430.200.090.040.02
DS191 (v1.18.1) July 2, 2018Product Specification
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
SymbolVCCOVOHVOLVODIFFVOCMVIDIFFVICM
DC Parameter
Supply Voltage
Output High Voltage for Q and QOutput Low Voltage for Q and QDifferential Output Voltage(Q–Q), Q = High (Q–Q), Q=High
Output Common-Mode VoltageDifferential Input Voltage(Q–Q), Q = High (Q–Q), Q=High
Input Common-Mode Voltage
Conditions
RT = 100Ω across Q and Q signalsRT = 100Ω across Q and Q signalsRT = 100Ω across Q and Q signalsMin2.375–0.7002471.0001000.300
Typ2.500––3501.2503501.200
Max2.6251.675–6001.4256001.500
UnitsVVVmVVmVV
RT = 100Ω across Q and Q signalsDS191 (v1.18.1) July 2, 2018Product Specification
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
Table 30:DDR3L Interface Switching Characteristics (800Mb/s)(1) (Cont’d)
SymbolTCKCA(6)Notes:
1.2.3.4.5.6.
Recommended VCCO_DDR=1.35V±5%.Measurement is taken from VREF to VREF.
Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crossesVIL(AC) to VREF of CLK.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crossesVIH(DC) to VREF of CLK.
Description
Command/address output hold time with respect to CLK
Min853
Max–
Unitsps
Table 31:LPDDR2 Interface Switching Characteristics (800Mb/s)(1)
SymbolTDQVALID(2)TDQDS(3)TDQDH(4)TDQSSTCACK(5)TCKCA(6)Notes:
1.2.3.4.5.6.
Description
Input data valid windowOutput DQ to DQS skewOutput DQS to DQ skewOutput clock to DQS skew
Command/address output setup time with respect to CLKCommand/address output hold time with respect to CLK
Min5001113180.91132363
Max–––1.10––
UnitspspspsTCKpsps
Recommended VCCO_DDR=1.2V±5%.Measurement is taken from VREF to VREF.
Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses VIL(AC)to VREF of CLK.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crossesVIH(DC) to VREF of CLK.
Table 32:LPDDR2 Interface Switching Characteristics (400Mb/s)(1)
SymbolTDQVALID(2)TDQDS(3)TDQDH(4)TDQSSTCACK(5)TCKCA(6)Notes:
1.2.3.4.5.6.
Recommended VCCO_DDR=1.2V±5%.Measurement is taken from VREF to VREF.
Measurement is taken from either the rising edge of DQ that crosses VIH(AC) or the falling edge of DQ that crosses VIL(AC) to VREF of DQS.Measurement is taken from either the rising edge of DQ that crosses VIL(DC) or the falling edge of DQ that crosses VIH(DC) to VREF of DQS.Measurement is taken from either the rising edge of CMD/ADDR that crosses VIH(AC) or the falling edge of CMD/ADDR that crosses VIL(AC)to VREF of CLK.
Measurement is taken from either the rising edge of CMD/ADDR that crosses VIL(DC) or the falling edge of CMD/ADDR that crossesVIH(DC) to VREF of CLK.
Description
Input data valid windowOutput DQ to DQS skewOutput DQS to DQ skewOutput clock to DQS skew
Command/address output setup time with respect to CLKCommand/address output hold time with respect to CLK
Min5005618520.91617918
Max–––1.08––
UnitspspspsTCKpsps
DS191 (v1.18.1) July 2, 2018Product Specification
FPGA可编程逻辑器件芯片XC7Z100-2FFG900I中文规格书
