FPGA可编程逻辑器件芯片EP2S3OF672I4N中文规格书 - 图文

Timing Model

Final timing numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under worst-case voltage and junction temperature conditions.Table4–52.StratixIIGX Device Timing Model Status

Device

EP2SGX30EP2SGX60EP2SGX90EP2SGX130

PreliminaryFinal

vvvv

I/O Timing Measurement Methodology

Different I/O standards require different baseline loading techniques for reporting timing delays. Altera characterizes timing delays with the required termination for each I/O standard and with 0pF (except for PCI and PCI-X which use 10pF) loading and the timing is specified up to the output pin of the FPGA device. The QuartusII software calculates the I/O timing for each I/O standard with a default baseline loading as specified by the I/O standards.

The following measurements are made during device characterization. Altera measures clock-to-output delays (tCO) at worst-case process,

minimum voltage, and maximum temperature (PVT) for default loading conditions shown in Table4–53. Use the following equations to calculate clock pin to output pin timing for StratixIIGX devices.

tCO from clock pin to I/O pin = delay from clock pad to I/O output

register + IOE output register clock-to-output delay + delayfrom output register to output pin + I/O output delaytxz/tzx from clock pin to I/O pin = delay from clock pad to I/O

output register + IOE output register clock-to-output delay +delay from output register to output pin + I/O output delay +output enable pin delaySimulation using IBIS models is required to determine the delays on the PCB traces in addition to the output pin delay timing reported by the QuartusII software and the timing model in the device handbook.1.

Simulate the output driver of choice into the generalized test setup,using values from Table4–53.Record the time to VMEAS.

2.

Stratix II GX Device Handbook, Volume 1

Table4–81.StratixIIGX IOE Programmable Delay on Row Pins

Minimum TimingMin Max OffsetOffset 0

1782

-3 SpeedGradeMin Offset 0

Note(1)

-3 SpeedGrade

Max Offset 3020

-4 SpeedGrade

-5 SpeedGrade

Parameter

Paths AffectedAvailable Settings

Max Min OffsetOffset 2876

0

Min Max Min Max OffsetOffsetOffset Offset 0

3212

0

3853

Unit

Input delay Pad to I/O from pin to dataout to internal logic arraycells

Input delay Pad to I/O from pin to input input register register

Delay from I/O output output register to register to pad output pin Output enable pin delay (1)

8 ps

64 0 2054 0 3270 0 3434 0 3652 0 4381 ps

2 0 332 0 500 0 525 0 559 0 670 ps

tXZ, tZX

2 0 320 0 483 0 507 0 539 0 647 ps

The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the latest version of the QuartusII software.

Default Capacitive Loading of Different I/O Standards

See Table4–82 for default capacitive loading of different I/O standards.Table4–82.Default Loading of Different I/O Standards for StratixIIGX Devices(Part 1 of2)

I/O Standard

LVTTLLVCMOS2.5 V1.8 V1.5 VPCIPCI-X

SSTL-2 ClassISSTL-2 ClassII

Capacitive Load

000 0 101000

Unit

pFpF pF pF pFpFpF pF

0 pF

Table4–92 shows the maximum output clock toggle rates for StratixIIGX device row pins.

Table4–92.Stratix II GX Maximum Output Clock Rate for Row Pins(Part 1 of2)I/O Standard

LVTTL

Drive Strength

4mA8mA12mA (1)

-3 Speed Grade

270 435 580 290 565 350 230 430 630 120 285 450 660 244 470 400 400 350 350 200 350 450 500 350 300 500 650 700 700 350 500 700

-4 Speed Grade

225 355 475 250 480 350 194 380 575 109 250 390 570 200 370 300 400 350 350 150 250 300 400 350 300 450 600 650 700 300 500 650

-5 Speed Grade

210 325 420 230 440 297 180 380 550 104 230 360 520 180 325 300 350 300 297 150 200 300 400 297 300 450 600 600 650 300 450 600

Unit

MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz

LVCMOS4mA8mA12mA (1)

2.5 V4mA8mA12mA (1)

1.8 V2mA4mA6mA8mA (1)

1.5 V

SSTL-2 Class ISSTL-2 Class IISSTL-18 Class I

2mA4mA (1)8mA12mA (1)16mA20mA (1)4mA6mA8mA10mA12mA (1)

1.8-V HSTL Class I

4mA6mA8mA10mA12mA (1)

1.5-V HSTL Class I

4mA6mA8mA (1)