Chapter 3:Boundary-Scan and JTAG Configuration
Capture-DR:
In this controller state, the data is parallel-loaded into the data registers selected by the current instruction on the rising edge of TCK.
Shift-Dr, Exit1-DR, Pause-DR, Exit2-DR, and Update-DR:
These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR, and Update-IR states in the Instruction path.
10TEST-LOGIC-RESET0RUN-TEST/IDLE1SELECT-DR-SCAN10CAPTURE-DR0SHIFT-DR1EXIT1-DR0PAUSE-DR01EXIT2-DR1UPDATE-DR10100101SELECT-IR-SCAN10CAPTURE-IR0SHIFT-IR1EXIT1-IR0PAUSE-IR1EXIT2-IR1UPDATE-IR00101NOTE: The value shown adjacent to each state transition in this figurerepresents the signal present at TMS at the time of a rising edge at TCK.
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Figure 3-2:Boundary-Scan TAP Controller
Virtex-5 devices support the mandatory IEEE 1149.1 commands, as well as several Xilinx vendor-specific commands. The EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,
IDCODE, USERCODE, and HIGHZ instructions are all included. The TAP also supports internal user-defined registers (USER1, USER2, USER3, and USER4) and configuration/readback of the device.
The Virtex-5 Boundary-Scan operations are independent of mode selection. The
Boundary-Scan mode in Virtex-5 devices overrides other mode selections. For this reason, Boundary-Scan instructions using the Boundary-Scan register (SAMPLE/PRELOAD, INTEST, and EXTEST) must not be performed during configuration. All instructions except the user-defined instructions are available before a Virtex-5 device is configured. After configuration, all instructions are available.
JSTART and JSHUTDOWN are instructions specific to the Virtex-5 architecture and
configuration flow. In Virtex-5 devices, the TAP controller is not reset by the PROGRAM_B pin and can only be reset by bringing the controller to the TLR state. The TAP controller is reset on power up.
For details on the standard Boundary-Scan instructions EXTEST, INTEST, and BYPASS, refer to the IEEE Standard.
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1
Boundary-Scan Architecture
Virtex-5 device registers include all registers required by the IEEE 1149.1 Standard. In addition to the standard registers, the family contains optional registers for simplified testing and verification (Table3-2).
Table 3-2:Virtex-5 Device JTAG Registers
Register NameBoundary-Scan RegisterInstruction RegisterBYPASS RegisterIdentification RegisterJTAG Configuration RegisterUSERCODE RegisterUser-Defined Registers (USER1, USER2, USER3, andUSER4)
Register Length3 bits per I/O10 or 14 bits
1 bit32 bits32 bits32 bitsDesign-specific
Description
Controls and observes input, output, and output enable
Holds current instruction OPCODE and captures internal device statusBypasses the deviceCaptures the Device ID
Allows access to the configuration bus when using the CFG_IN or CFG_OUT instructions
Captures the user-programmable codeDesign-specific
Boundary-Scan Register
The test primary data register is the Boundary-Scan register. Boundary-Scan operation is independent of individual IOB configurations. Each IOB, bonded or unbonded, starts as bidirectional with 3-state control. Later, it can be configured to be an input, output, or 3-state only. Therefore, three data register bits are provided per IOB (Figure3-3).
When conducting a data register (DR) operation, the DR captures data in a parallel fashion during the CAPTURE-DR state. The data is then shifted out and replaced by new data during the SHIFT-DR state. For each bit of the DR, an update latch is used to hold the input data stable during the next SHIFT-DR state. The data is then latched during the UPDATE-DR state when TCK is Low.
The update latch is opened each time the TAP controller enters the UPDATE-DR state. Care is necessary when exercising an INTEST or EXTEST to ensure that the proper data has been latched before exercising the command. This is typically accomplished by using the SAMPLE/PRELOAD instruction.
Internal pull-up and pull-down resistors should be considered when test vectors are being developed for testing opens and shorts. The HSWAPEN pin determines whether the IOB has a pull-up resistor. Figure3-3 is a representation of Virtex-5 Boundary-Scan architecture.
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Chapter 3:Boundary-Scan and JTAG Configuration
Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1532
ISC Modal States
Any non-test instruction,but ISC_ENABLEexecutedISC_ENABLE is executedUnprogrammed(0,0)TLR & ISC_Done is clearISC_Accessed(1,X)Any non-testinstruction, butISC_DISABLEexecutedAny non-test instruction, but ISC_DISABLE loaded and ISC_DONE is clearISC_Done is clearPowerUP TLR and ISC_Doneis setISC_ENABLEexecutedISC_DISABLEexecutedISC_Done is setAny non-test instruction,but ISC_ENABLEexecutedISC_DISABLEloadedOperational(0,1)Any non-test instruction, but ISC_DISABLE loadedand ISC_DONE is setISC Complete(0,X)(ISC_Enabled, ISC_Done)UG191_c3_08_050406
Figure 3-8:ISC Modal States
Once the device is powered up, it goes to the Unprogrammed state. The I/Os are all either 3-stated or pulled up. When ISC_ENABLE is successfully executed, the ISC_Enabled
signal is asserted, and the device moves to the ISC_Accessed state. When the device movesto the ISC_Accessed state from the Operational state, the shutdown sequence is executed.The I/Os are all either 3-stated or pulled up.
The startup sequence is executed when in the ISC_Accessed state. At the end of the startup sequence, ISC_Enabled is cleared and the device moves to ISC_Complete. The minimum clock cycle requirement is the number of clock cycles required to complete the startup sequence. At the completion of the minimum required clock cycles, ISC_Enabled is deasserted.
Whether the startup sequence is successful or not is determined by CRC or configuration error status from the configuration processor. If the startup is completed, ISC_Done is asserted; otherwise, ISC_Done stays Low. The I/Os are either 3-stated or pulled up.When ISC_Done is set in ISC_Complete state, the device moves to the Operational state. Otherwise, if ISC_Done is clear, the device moves to the Unprogrammed state. However, if the TAP controller goes to the TLR state while the device is in ISC_Accessed state, and if ISC_Done is set, then the device moves to the Operational state.
Though Operational, the I/O is not active yet because the startup sequence has not been performed. The startup sequence has to be performed in the Operational state to bring the I/O active.
Virtex-5 FPGA Configuration Guide
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Chapter 3:Boundary-Scan and JTAG Configuration
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
Chapter 5:Dynamic Reconfiguration Port (DRP)
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
FPGA可编程逻辑器件芯片XC2S200E-7FTG256I中文规格书 - 图文
