MEMORY存储芯片N25Q128A11ESE40F中文规格书 - 图文

Burst Type

Accesses within a given burst may be programmed to be either sequential or inter-leaved. The burst type is selected via bit M3, as shown in Figure 36. The ordering of ac-cesses within a burst is determined by the burst length, the burst type, and the startingcolumn address, as shown in Table 41. DDR2 SDRAM supports 4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode, full interleaved address ordering is suppor-ted; however, sequential address ordering is nibble-based.

Table 41: Burst Definition

Burst Length4Starting Column Address(A2, A1, A0)0 0 00 0 10 1 00 1 180 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1Order of Accesses Within a BurstBurst Type = Sequential0, 1, 2, 31, 2, 3, 02, 3, 0, 13, 0, 1, 20, 1, 2, 3, 4, 5, 6, 71, 2, 3, 0, 5, 6, 7, 42, 3, 0, 1, 6, 7, 4, 53, 0, 1, 2, 7, 4, 5, 64, 5, 6, 7, 0, 1, 2, 35, 6, 7, 4, 1, 2, 3, 06, 7, 4, 5, 2, 3, 0, 17, 4, 5, 6, 3, 0, 1, 2Burst Type = Interleaved0, 1, 2, 31, 0, 3, 22, 3, 0, 13, 2, 1, 00, 1, 2, 3, 4, 5, 6, 71, 0, 3, 2, 5, 4, 7, 62, 3, 0, 1, 6, 7, 4, 53, 2, 1, 0, 7, 6, 5, 44, 5, 6, 7, 0, 1, 2, 35, 4, 7, 6, 1, 0, 3, 26, 7, 4, 5, 2, 3, 0, 17, 6, 5, 4, 3, 2, 1, 0Operating Mode

The normal operating mode is selected by issuing a command with bit M7 set to “0,”and all other bits set to the desired values, as shown in Figure 36 (page 80). When bit M7is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1”places the DDR2 SDRAM into a test mode that is only used by the manufacturer andshould not be used. No operation or functionality is guaranteed if M7 bit is “1.”

DLL RESET

DLL RESET is defined by bit M8, as shown in Figure 36. Programming bit M8 to “1” willactivate the DLL RESET function. Bit M8 is self-clearing, meaning it returns back to avalue of “0” after the DLL RESET function has been issued.

Anytime the DLL RESET function is used, 200 clock cycles must occur before a READcommand can be issued to allow time for the internal clock to be synchronized with theexternal clock. Failing to wait for synchronization to occur may result in a violation ofthe tAC or tDQSCK parameters.

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Preliminary

1Gb: x4, x8, x16 DDR2 SDRAMExtended Mode Register (EMR)

DLL Enable/Disable

The DLL may be enabled or disabled by programming bit E0 during the LM command,as shown in Figure 38 (page 84). These specifications are applicable when the DLL is en-abled for normal operation. DLL enable is required during power-up initialization andupon returning to normal operation after having disabled the DLL for the purpose ofdebugging or evaluation. Enabling the DLL should always be followed by resetting theDLL using the LM command.

The DLL is automatically disabled when entering SELF REFRESH operation and is auto-matically re-enabled and reset upon exit of SELF REFRESH operation.

Anytime the DLL is enabled (and subsequently reset), 200 clock cycles must occur be-fore a READ command can be issued to allow time for the internal clock to synchronizewith the external clock. Failing to wait for synchronization to occur may result in a vio-lation of the tAC or tDQSCK parameters.

Anytime the DLL is disabled and the device is operated below 25 MHz, any AUTO RE-FRESH command should be followed by a PRECHARGE ALL command.

Output Drive Strength

The output drive strength is defined by bit E1, as shown in Figure 38. The normal drivestrength for all outputs is specified to be SSTL_18. Programming bit E1 = 0 selects nor-mal (full strength) drive strength for all outputs. Selecting a reduced drive strength op-tion (E1 = 1) will reduce all outputs to approximately 45 to 60 percent of the SSTL_18drive strength. This option is intended for the support of lighter load and/or point-to-point environments.

DQS# Enable/Disable

The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the dif-ferential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a single-ended mode and the DQS# ball is disabled. When disabled, DQS# should be left float-ing; however, it may be tied to ground via a 20Ω to 10kΩ resistor. This function is alsoused to enable/disable RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled (E10 =0), then both DQS# and RDQS# will be enabled.

RDQS Enable/Disable

The RDQS ball is enabled by bit E11, as shown in Figure 38. This feature is only applica-ble to the x8 configuration. When enabled (E11 = 1), RDQS is identical in function andtiming to data strobe DQS during a READ. During a WRITE operation, RDQS is ignoredby the DDR2 SDRAM.

Output Enable/Disable

The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 38. When ena-bled (E12 = 0), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) function normally. Whendisabled (E12 = 1), all outputs (DQ, DQS, DQS#, RDQS, RDQS#) are disabled, thus re-moving output buffer current. The output disable feature is intended to be used duringIDD characterization of read current.

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Preliminary

1Gb: x4, x8, x16 DDR2 SDRAMExtended Mode Register (EMR)

On-Die Termination (ODT)

ODT effective resistance, RTT(EFF), is defined by bits E2 and E6 of the EMR, as shown inFigure 38 (page 84). The ODT feature is designed to improve signal integrity of the

memory channel by allowing the DDR2 SDRAM controller to independently turn on/offODT for any or all devices. RTT effective resistance values of 50Ω????Ω, and 150Ω are se-lectable and apply to each DQ, DQS/DQS#, RDQS/RDQS#, UDQS/UDQS#, LDQS/

LDQS#, DM, and UDM/LDM signal. Bits (E6, E2) determine what ODT resistance is en-abled by turning on/off sw1, sw2, or sw3. The ODT effective resistance value is selectedby enabling switch sw1, which enables all R1 values that are 150Ω each, enabling an ef-fective resistance of 75Ω (RTT2 [EFF] = R2/2). Similarly, if sw2 is enabled, all R2 values thatare 300Ω each, enable an effective ODT resistance of 150Ω (RTT2[EFF] = R2/2). Switch sw3enables R1 values of 100Ω, enabling effective resistance of 50Ω. Reserved states shouldnot be used, as an unknown operation or incompatibility with future versions may re-sult.

The ODT control ball is used to determine when RTT(EFF) is turned on and off, assumingODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT inputball are only used during active, active power-down (both fast-exit and slow-exitmodes), and precharge power-down modes of operation.

ODT must be turned off prior to entering self refresh mode. During power-up and initi-alization of the DDR2 SDRAM, ODT should be disabled until the EMR command is is-sued. This will enable the ODT feature, at which point the ODT ball will determine theRTT(EFF) value. Anytime the EMR enables the ODT function, ODT may not be drivenHIGH until eight clocks after the EMR has been enabled (see Figure 81 (page 131) forODT timing diagrams).

Off-Chip Driver (OCD) Impedance Calibration

The OFF-CHIP DRIVER function is an optional DDR2 JEDEC feature not supported byMicron and thereby must be set to the default state. Enabling OCD beyond the defaultsettings will alter the I/O drive characteristics and the timing and output I/O specifica-tions will no longer be valid (see Initialization section for proper setting of OCD de-faults).

Posted CAS Additive Latency (AL)

Posted CAS additive latency (AL) is supported to make the command and data bus effi-cient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, asshown in Figure 38. Bits E3–E5 allow the user to program the DDR2 SDRAM with an ALof 0, 1, 2, 3, 4, 5, or 6 clocks. Reserved states should not be used as an unknown opera-tion or incompatibility with future versions may result.

In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issuedprior to tRCD (MIN) with the requirement that AL ≤ tRCD (MIN). A typical applicationusing this feature would set AL = tRCD (MIN) - 1 × tCK. The READ or WRITE commandis held for the time of the AL before it is issued internally to the DDR2 SDRAM device.RL is controlled by the sum of AL and CL; RL = AL + CL. WRITE latency (WL) is equal toRL minus one clock; WL = AL + CL - 1 × tCK. An example of RL is shown in Figure 39(page 87). An example of a WL is shown in Figure 40 (page 87).

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Preliminary

1Gb: x4, x8, x16 DDR2 SDRAMExtended Mode Register (EMR)

Figure 39: READ Latency

T0T1T2T3T4T5T6T7T8CK#CKCommandDQS, DQS#ACTIVE nREAD nNOPNOPNOPNOPNOPNOPNOPtRCD (MIN)DQAL = 2RL = 5Transitioning Data

Don’t Care

CL = 3DO nDO n + 1DO n + 2DO n + 3Notes:1.BL = 4.

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Preliminary

1Gb: x4, x8, x16 DDR2 SDRAMExtended Mode Register 2 (EMR2)

Extended Mode Register 2 (EMR2)

The extended mode register 2 (EMR2) controls functions beyond those controlled bythe mode register. Currently all bits in EMR2 are reserved, except for E7, which is usedin commercial or high-temperature operations, as shown in Figure 41. The EMR2 is pro-grammed via the LM command and will retain the stored information until it is pro-grammed again or until the device loses power. Reprogramming the EMR will not alterthe contents of the memory array, provided it is performed correctly.

Bit E7 (A7) must be programmed as 1 to provide a faster refresh rate on IT and AT devi-ces if TC exceeds 85°C.

EMR2 must be loaded when all banks are idle and no bursts are in progress, and thecontroller must wait the specified time tMRD before initiating any subsequent opera-tion. Violating either of these requirements could result in an unspecified operation.

Figure 41: EMR2 Definition

12BA2BA1BA0AnA12A11A10A9A8A7A6A5A4A3A2A1A0Address bus1601514nMRS012110010987600SRT00E70154320000100 0Extended mode register (Ex)E15E1400110101Mode Register SetMode register (MR)Extended mode register (EMR)Extended mode register (EMR2)Extended mode register (EMR3)SRT Enable1X refresh rate (0°C to 85°C)2X refresh rate (>85°C)Notes:

1.E16 (BA2) is only applicable for densities ≥1Gb, reserved for future use, and must be pro-grammed to 0.

2.Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-served for future use and must be programmed to 0.

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