4.PIN DESCRIPTIONS
4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. When /CS is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure 58). If needed a pull-up resister on the /CS pin can be used to accomplish this.
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25Q64JV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and the /HOLD pin becomes IO3.
4.3 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware protected. The /WP pin is active low.
4.4 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3. See Figure 1a-c for the pin configuration of Quad I/O operation.
4.5 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. (\Operations\
4.6 Reset (/RESET)(1)
A dedicated hardware /RESET pin is available on SOIC-16 and TFBGA packages. When it’s driven low for a minimum period of ~1μS, this device will terminate any external or internal operations and return to its power-on state. Note:
1. Hardware /RESET pin is available on SOIC-16 or TFBGA; please contact Winbond for this package.
Publication Release Date: March 27, 2018
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5.BLOCK DIAGRAM
SFDP Register000000h 0000FFhSecurity Register 1 -3003000h 002000h 001000h 0030FFh 0020FFh 0010FFhBlock SegmentationxxFF00h xxFFFFh? Sector 15 (4KB) ?xxF000h xxF0FFhxxEF00h xxEFFFh? Sector 14 (4KB) ?xxE000h xxE0FFhxxDF00h xxDFFFh? Sector 13 (4KB) ?xxD000h xxD0FFh7FFF00h 7FFFFFh?Block 127 (64KB) ?7F0000h 7F00FFhxx1F00h xx1FFFh? Sector 1 (4KB) ?xx1000h xx10FFhxx0F00h xx0FFFh? Sector 0 (4KB) ?xx0000h xx00FFh40FF00h 40FFFFh?Block 64 (64KB) ?400000h 4000FFh3FFF00h 3FFFFFh?Block 63 (64KB) ?3F0000h 3F00FFh???20FF00h 20FFFFh?Block 32 (64KB) ?200000h 2000FFh/WP (IO2)Write ControlLogicStatusRegister1FFF00h 1FFFFFh?Block 31 (64KB) ?1F0000h 1F00FFh???00FF00h ?000000h Block 0 (64KB) 00FFFFh ? 0000FFhEndingPage AddressHigh VoltageGenerators/HOLD (IO3)CLK/CSPage AddressLatch / CounterSPICommand &Control LogicBeginningPage AddressColumn DecodeAnd 256-Byte Page BufferDataDI (IO0)DO (IO1)Byte AddressLatch / Counter Figure 2. W25Q64JV Serial Flash Memory Block Diagram
Publication Release Date: March 27, 2018
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WW25Q4FV256Q64JVxx2F00h xx2FFFh? Sector 2 (4KB) ?xx2000h xx20FFhWrite Protect Logic and Row Decode??????W25Q64JV
Publication Release Date: March 27, 2018
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6.5 Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern, the W25Q64JV provides several means to protect the data from inadvertent writes.
Write Protect Features
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Device resets when VCC is below thresholdTime delay write disable after Power-up
Write enable/disable instructions and automatic write disable after erase or programSoftware and Hardware (/WP pin) write protection using Status RegistersAdditional Individual Block/Sector Locks for array protectionWrite Protection using Power-down instruction
Lock Down write protection for Status Register until the next power-up
One Time Program (OTP) write protection for array and Security Registers using Status Register*
*Note: This feature is available upon special flow. Please contact Winbond for details.
Upon power-up or at power-down, the W25Q64JV will maintain a reset condition while VCC is below the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 43). While reset, all operations are disabled and no instructions are recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached, and it must also track the VCC supply level at power-down to prevent adverse command sequence. If needed a pull-up resister on /CS can be used to accomplish this. After power-up the device is automatically placed in a write-disabled state with the Status Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting the Status Register Protect (SRP, SRL) and Block Protect (CMP, TB, BP[3:0]) bits. These settings allow a portion or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See Status Register section for further information. Additionally, the Power-down instruction offers an extra level of write protection as all instructions are ignored except for the Release Power-down instruction.
The W25Q64JV also provides another Write Protect method using the Individual Block Locks. Each 64KB block (except the top and bottom blocks, total of 126 blocks) and each 4KB sector within the top/bottom blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is 0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or Program commands issued to the corresponding sector or block will be ignored. When the device is powered on, all Individual Block Lock bits will be 1, so the entire memory array is protected from Erase/Program. An “Individual Block Unlock (39h)” instruction must be issued to unlock any specific sector or block.
The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be used. When WPS=0 (factory default), the device will only utilize CMP, SEC, TB, BP[2:0] bits to protect specific areas of the array; when WPS=1, the device will utilize the Individual Block Locks for write protection.
Publication Release Date: March 27, 2018
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7.
STATUS AND CONFIGURATION REGISTERS
Three Status and Configuration Registers are provided for W25Q64JV. The Read Status Register-1/2/3 instructions can be used to provide status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status, Erase/Program Suspend status, output driver strength, power-up. The Write Status Register instruction can be used to configure the device write protection features, Quad SPI setting, Security Register OTP locks, and output driver strength. Write access to the Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRL), the Write Enable instruction, and during Standard/Dual SPI operations
7.1 Status Registers
S7 SRPSTATUS REGISTER PROTECT (volatile/non-volatile)S6 SECS5 TBS4 BP2 S3 BP1 S2 BP0 S1 S0 WELBUSYSECTOR PROTECT(volatile/non-volatile)TOP/BOTTOM PROTECT(volatile/non-volatile)BLOCK PROTECT BITS(volatile/non-volatile)WRITE ENABLE LATCHWRITE IN PROGRESSFigure 4a. Status Register-1
Erase/Write In Progress (BUSY) – Status Only
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or Erase/Program Security Register instruction. During this time the device will ignore further instructions except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status/security register instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.
Write Enable Latch (WEL) – Status Only
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and Program Security Register.
Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be protected from Program and Erase instructions (see Status Register Memory Protection table). The factory default setting for the Block Protection Bits is 0, none of the array protected.
Publication Release Date: March 27, 2018
Revision J