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半导体传感器AD7706BRZ中文规格书 - 图文

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AD7705/AD7706

SPECIFICATIONS

VDD = 3 V or 5 V, REF IN(+) = 1.225 V with VDD = 3 V, and 2.5 V with VDD = 5 V; REF IN(?) = GND; MCLK IN = 2.4576 MHz, unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted. Table 1. ParameterSTATIC PERFORMANCE No Missing Codes Output Noise Integral Nonlinearity2 Unipolar Offset Error3Unipolar Offset Drift4Bipolar Zero Error3Bipolar Zero Drift4 Positive Full-Scale Error3, 5Full-Scale Drift4, 6Gain Error3, 7Gain Drift4, 8Bipolar Negative Full-Scale Error2 Bipolar Negative Full-Scale Drift4 ANALOG INPUTS/REFERENCE INPUTS Common-Mode Rejection (CMR)2VDD = 5 V Gain = 1 Gain = 2 Gain = 4 Gain = 8 to 128 VDD = 3 V Gain = 1 Gain = 2 Gain = 4 Gain = 8 to 128 Normal-Mode 50 Hz Rejection2 Normal-Mode 60 Hz Rejection2 Common-Mode 50 Hz Rejection2 Common-Mode 60 Hz Rejection2 Absolute/Common-Mode REF IN Voltage2 Absolute/Common-Mode AIN Voltage2, 9, 10Absolute/Common-Mode AIN Voltage2, 9 AIN DC Input Current2AIN Sampling Capacitance2AIN Differential Voltage Range11 BVersion116 See Table 5 and Table 7 ±0.003 0.50.5 0.1 0.50.5±0.003 1 0.6 UnitBits min Conditions/CommentsGuaranteed by design, filter notch < 60 Hz Depends on filter cutoffs and selected gain Filter notch < 60 Hz, typically ±0.0003% % of FSR max μV/°CtypμV/°C typ μV/°C typ μV/°Ctypppm of FSR/°C typ % of FSR typ μV/°C typ μV/°C typ For gains 1, 2, and 4 For gains 8, 16, 32, 64, and 128 Typically ±0.001% For gains of 1 to 4 For gains of 8 to 128 Specifications for AIN and REF IN, unless otherwise noted 96 105 110 130 105 110 120 130 98 98 150 150 GND to VDD GND ? 100 mV VDD + 30 mV GND + 50 mV dB typ dB typ dB typ dB typ dB typ dB typ dB typ dB typ dB typ dB typ dB typ dB typ V min to V max V min V max V min For filter notches of 25 Hz, 50 Hz, ±0.02 × fNOTCH For filter notches of 20 Hz, 60 Hz, ±0.02 × fNOTCH For filter notches of 25 Hz, 50 Hz, ±0.02 × fNOTCH For filter notches of 20 Hz, 60 Hz, ±0.02 × fNOTCH BUF bit of setup register = 0 BUF bit of setup register = 1 VDD ? 1.5 V V max 1nAmax10Fp max0 to +VREF/gain12 nom ±VREF/gain nom Unipolar input range (B/U bit of setup register = 1) Bipolar input range (B/U bit of setup register = 0) Rev. C | Page 5 of 44

AD7705/AD7706

Parameter

AIN Input Sampling Rate, fS Reference Input Range

REF IN(+) ? REF IN(?) Voltage REF IN(+) ? REF IN(?) Voltage REF IN Input Sampling Rate, fS LOGIC INPUTS Input Current

All Inputs, Except MCLK IN MCLK IN

All Inputs, Except SCLK and MCLK IN Input Low Voltage, VINL

BVersion1

Gain × fCLKIN/64 fCLKIN/8 1/1.75 1/3.5 fCLKIN/64

Unit

Conditions/CommentsFor gains of 1 to 4 For gains of 8 to 128

VDD = 2.7 V to 3.3 V

VREF = 1.225 ± 1% for specified performance VDD = 4.75 V to 5.25 V

VREF = 2.5 ± 1% for specified performance

V min/V max V min/V max

±1 ±10 μA max μA max Typically ±20 nA Typically ±2 μA

Input High Voltage, VINH

SCLK Only (Schmitt-Triggered Input) VT+ VT?

VT+ ? VT?

SCLK Only (Schmitt-Triggered Input) VT+ VT?

VT+ ? VT? MCLK IN Only

Input Low Voltage, VINLInput High Voltage, VINHMCLK IN Only

Input Low Voltage, VINLInput High Voltage, VINH

LOGIC OUTPUTS (Including MCLK OUT) Output Low Voltage, VOL0.4V maxISINK = 800 μA, except for MCLK OUT;13 VDD = 5 V Output Low Voltage, VOL 0.4V maxISINK = 100 μA, except for MCLK OUT;13 VDD = 3 V Output High Voltage, VOH4V minISOURCE = 200 μA, except for MCLK OUT;13 VDD = 5 V Output High Voltage, VOH VDD ? 0.6 V min ISOURCE = 100 μA, except for MCLK OUT;13 VDD = 3 V Floating State Leakage Current ±10 μA max Floating State Output Capacitance14 9 Fp typ Data Output Coding Binary Unipolar mode

Offset binary Bipolar mode

SYSTEM CALIBRATION Positive Full-Scale Limit15(1.05 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) Negative Full-Scale Limit15?(1.05 × VREF)/gain V max Gain is the selected PGA gain (1 to 128)

15

Offset Limit?(1.05 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) Input Span16(0.8 × VREF)/gain V min Gain is the selected PGA gain (1 to 128)

(2.1 × VREF)/gain V max Gain is the selected PGA gain (1 to 128)

0.8V maxVDD = 5 V 0.4 V max VDD = 3 V 2.0V minVDD = 3 V and 5 V

VDD = 5 V nominal

1.4/3 V min/V max 0.8/1.4 V min/V max 0.4/0.8 V min/V max

VDD = 3 V nominal

1/2 V min/V max 0.4/1.1 V min/V max 0.375/0.8 V min/V max

VDD = 5 V nominal

0.8V max3.5V min

VDD = 3 V nominal

0.4V max2.5V min

Rev. C | Page 6 of 44

半导体传感器AD7706BRZ中文规格书 - 图文

AD7705/AD7706SPECIFICATIONSVDD=3Vor5V,REFIN(+)=1.225VwithVDD=3V,and2.5VwithVDD=5V;REFIN(?)=GND;MCLKIN=2.4576MHz,unlessotherwisenoted.Allspecific
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