Serial-to-Parallel/Parallel-to-Serial Converters andLoad-Switch Controllers with SMBus InterfaceMAX1661/MAX1662/MAX1663ABSOLUTE MAXIMUM RATINGS
VCCto GND..............................................................-0.3V to +6VI/O to GND (I/O1, I/O2, I/O3)..................................-0.3V to +30VI/O Sink Current (I/O1, I/O2, I/O3),
Internally Limited.............................................-1mA to +50mADigital Inputs to GND (SMBCLK, SMBDATA,
SMBSUS, ALERT).................................................-0.3V to +6VADD to GND...............................................-0.3V to (VCC+ 0.3V)SMBDATA Current, ALERTCurrent....................-1mA to +50mA
Continuous Power Dissipation (TA= +70°C)
10-pin μMAX (derate 5.6mW/°C above +70°C)...........444mWOperating Temperature Range
MAX166_EUB..................................................-40°C to +85°CStorage Temperature Range.............................-65°C to +160°CLead Temperature (soldering, 10sec).............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.ELECTRICAL CHARACTERISTICS
(VCC= +2.7V to +5.5V, TA= TMINto TMAX, unless otherwise noted. Typical values are for TA= +25°C.) (Note 1)
PARAMETERInput Voltage RangeSupply CurrentUndervoltage Lockout/ Power-On Reset ThresholdI/O Sink CurrentI/O Current LimitThermal ShutdownI/O Leakage CurrentDigital Input Current SMBus Logic Input Voltage RangeLogic Input High VoltageLogic Input Low VoltageSMBDATA Output Low SinkCurrentALERTOutput Low Sink CurrentALERTOutput Leakage CurrentSMBus Input CapacitanceSMBus Clock FrequencySMBCLK High TimeSMBCLK Low TimetHIGHtLOWStatic condition; SMBDATA, SMBCLK, ADD,ALERT= VCCor GND (Note 2)VCCfallingVI/O_= 0.4V, VCC= 2.7V or 5.5VVI/O_= 1.0V, VCC= 4.5VI/O1, I/O2, or I/O3; VCC= 4.5VTypical hysteresis of 10°CVI/O_= 28V, high-impedance stateVI/O_= 0V, VCC; high-impedance stateVSMBDATA, VSMBCLK, VSMBSUS, VADD= 0V, VCCVCC= 2.7V to 5.5V; SMBDATA, SMBCLK, SMBSUSI/O_, SMBSUS, SMBCLK, SMBDATAI/O_, SMBSUS, SMBCLK, SMBDATAVSMBDATA= 0.6VVALERT= 0.4VVALERT= 5.5V, high-Z stateSMBCLK, SMBDATA(Notes 3, 4)Measured between the 90% level of the risingedge and the 90% level of the falling edgeMeasured between the 10% level of the fallingedge and the 10% level of the rising edge44.75100611-1-102.40.81.2281513201400.50.55115.550SYMBOLCONDITIONSMIN2.731.6TYPMAX5.5102.5UNITSVμAVmAmA°CμAμAVVVmAmAμApFkHzμsμsSerial-to-Parallel/Parallel-to-Serial Converters andLoad-Switch Controllers with SMBus InterfaceELECTRICAL CHARACTERISTICS (continued)
(VCC= +2.7V to +5.5V, TA= TMINto TMAX, unless otherwise noted. Typical values are for TA= +25°C.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSStart-Condition Setup TimetSU:STAMeasured from 90% of the SMBCLK risingedge to 90% of the SMBDATA falling edge 4.7μsMeasured from 10% of the falling edge Start-Condition Hold Time tHD:STAof SMBDATA to 90% of the falling edge of4μsSMBCLK SMBus Stop-Condition SetupMeasured from 90% of the rising edge TimetSU:STOof SMBCLK to 10% of the rising edge of 4μsSMBDATASMBDATA Valid to SMBCLK10% or 90% of SMBDATA VCC= 4.5V 500Rising Edge Time, SlavetSU:DATto 10% of the rising edge to 5.5VnsClocking in Dataof SMBCLKVCC= 2.7V to 4.5V1000SMBCLK Falling Edge to SMBDATA Transition Hold TimetHD:DAT(Notes 4, 5)0μsSMBCLK Falling Edge to Tested with a 10k?pull-up resistor on SMBus Data Valid Time tDVSMBDATA (Note 6) 1μsSMBus Bus-Free TimetBUFBetween stop and start conditions (Note 7)4.7μsSMBus Write to I/O_Measured from SMBCLK rising edge to 10%Propagation DelaytP:I/Oor 90% of I/O (Note 4)100nsI/O Data Valid to SMBCLKMeasured from 10% or 90% of VI/Oto 10% ofRising-Edge Setup TimetSU:I/Othe rising edge of SMBCLK (Note 8)15μsI/O Data Hold TimetHD:I/O(Note 8)0μsSTART-STOP Software-InterruptMeasured from the 10% point of the fallingPulse WidthtLOW:SSedge of SMBDATA to the 10% point of the 101530μsrising edge of SMBDATA (Note 7)Note 1:Specifications from 0°C to -40°C are guaranteed by design, not production tested.Note 2:Supply current is specified for static state only.
Note 3:The SMBus logic block is a static design that works with clock frequencies down to DC. While slow operation is possible, it
violates the 10kHz minimum clock frequency of the SMBus specifications, and may monopolize the bus.
Note 4:Refer to Figures 2a and 2b for SMBus timing parameter definitions (write and read diagrams).
Note 5:A transition must internally provide a hold time of 300ns to accommodate for the undefined region of the falling edge.Note 6:Refer to Figure 3 for the acknowledge timing diagram and tDVparameter definition.Note 7:Refer to Figure 5 for START-STOP interrupt timing diagrams and parameter definitions.Note 8:Refer to Figure 4 for I/O setup and hold timing parameter definitions.
MAX1661/MAX1662/MAX1663
MEMORY存储芯片MAX708TCSA+T中文规格书 - 图文
