Chapter6
Configuration Details
Configuration Memory Frames
Virtex?-5 FPGA configuration memory is arranged in frames that are tiled about the device. These frames are the smallest addressable segments of the Virtex-5 configuration memory space, and all operations must therefore act upon whole configuration frames. Virtex-5 frame counts and configuration sizes are shown in Table6-1. Depending on BitGen options, additional overhead exists in the configuration bitstream. The exact
bitstream length is available in the rawbits file (.rbt) created by using the \bitgen or selecting \options popup in ISE. Bitstream length (words) are roughly equal to the configuration array size (words) plus configuration overhead (words). Bitstream length (bits) are roughly equal to the bitstream length in words times 32.
Table 6-1:
Device
Virtex-5 Device Frame Count, Frame Length, Overhead, and Bitstream Size
Non-Configuration
Frames(1)
Configuration Frames
Total Device Frames
Frame Lengths in Configuration Array Bitstream Overhead
Words(2)Size in Words(3)in Words(4)
LX30LX50LX85LX110LX155LX220LX330LX20TLX30TLX50TLX85TLX110TLX155TLX220TLX330TSX35TSX50T
1722584265688001,0401,5601261842764445928081,0641,596244366
6,3769,56416,64422,19232,54440,49660,7443,7627,13610,70417,78423,71232,80042,01663,02410,16815,252
6,5489,82217,07022,76033,34441,53662,3043,8887,32010,98018,22824,30433,60843,08064,62010,41215,618
4141414141414141414141414141414141
261,416392,124682,404909,8721,334,3041,660,3362,490,504154,242292,576438,864729,144972,1921,344,8001,722,6562,583,984416,888625,332
272272272272272272272272272272272272272272272272272
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
Frame Addressing
Table 6-16:Frames (Minor Addresses) per Column
BlockCLBDSPBlock RAM
IOBClock ColumnClock Column
Number of Frames
3628305444
The frames are numbered from left to right, starting with 0. For each block, except the clock column, frames numbered 0 to 25 access the Interconnect for that column. For all blocks, except the CLB and the clock column, frames numbered 26 and 27 access the Interface for that column. All other frames are specific to that block.
Block RAM Contents
The actual memory contents of the block RAM is configured in a different section of the address space for two reasons. First, access to the configuration frames is done differently for block RAM contents than for regular configuration frames. Second, it is easy to skip configuration of the block RAM contents if it is not required, which can significantly reduce the size of the bitstream.
When accessing the block RAM contents, the block RAM major address must be used (from the second sequence of major addresses). This major address is probably different from the normal major address used to access the configuration of the block RAM and of its interconnect. The block RAM contains 128 frames per column and HCLK row.
Interconnect and Block Special Frame
There is one special frame per column, which contains configuration bits used for partial reconfiguration. Because few designs use partial reconfiguration, this section of the address space can be skipped for normal use.
This special frame is accessed with a minor address of 0. Only the 16 HCLK bits are used, and all other bits are assumed to be 0. Thus a special frame contains only 4 bits of data, because the other 12 HCLK bits are the 12 ECC bits, as shown in Table6-17.Table 6-17:
Special Frame Bits
Use
Unused
Gates GTS_CFG_B in IOB column onlyGates GCAP and GRESTORE in all columnsGates GHIGH_B and GWE in all columns12 ECC bits (assumes that all other bits are 0)
Bit Numbers
<15><14><13><12><11:0>
The “Partial Reconfiguration” section provides more details.
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
Chapter 6:Configuration Details
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
Readback Command Sequences
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2024
Chapter 7:Readback and Configuration Verification
Table 7-5:Status Register Readback Command Sequence (JTAG)
Set and Hold
Step
Description
Clock five 1s on TMS to bring the device to the TLR state.1
Move into the RTI state.Move into the Select-IR state.Move into the Shift-IR state.
Shift the first nine bits of the CFG_IN instruction, LSB first.2
Shift the MSB of the CFG_IN instruction while exiting SHIFT-IR.
Move into the SELECT-DR state.Move into the SHIFT-DR state.
TDI
XXXX
TMS
10100110
# of Clocks (TCK)
51229122
111000101
(CFG_IN)
1XX
a:0xAA995566b:0x20000000c:0x2800E001d:0x20000000
Shift configuration packets into the CFG_IN data register, MSB first.3
0159
e:0x20000000
Shift the LSB of the last configuration packet while exiting SHIFT-DR.Move into the SELECT-IR state.Move into the SHIFT-IR state.
Shift the first nine bits of the CFG_OUT instruction, LSB first.4
Shift the MSB of the CFG_OUT instruction while exiting Shift-IR.
Move into the SELECT-DR state.Move into the SHIFT-DR state.
Shift the contents of the STAT register out of the CFG_OUT data register.
Shift the last bit of the STAT register out of the CFG_OUT data register while exiting SHIFT-DR.
Move into the Select-IR state.Move into the Shift-IR State.6
Reset the TAP Controller.
0XX
11001100
132912231
111000100
(CFG_OUT)
1XX
0xSSSSSSSS
5
SXXX
1101
1325
The packets shifted in to the JTAG CFG_IN register are identical to the packets shifted in through the SelectMAP interface when reading the STAT register through SelectMAP.
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2024
FPGA可编程逻辑器件芯片XC2S15-5FG256I中文规格书 - 图文
