FPGA可编程逻辑器件芯片XQR4036XL-3CB228M中文规格书 - 图文

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DS714 (v2.2) January 17, 2011Product Specification

Virtex-5Q FPGA Electrical Characteristics

Defense-grade Virtex?-5Q FPGAs are available in -2I, -1I, and -1M (only FX70T and FX100T devices in -1M) speed grades, with -2I having the highest performance. Virtex-5Q FPGA DC and AC characteristics are specified for the industrial temperature range. Except the operating

temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade.

All supply voltage and junction temperature specifications are representative of worst-case conditions. The

parameters included are common to popular designs and typical applications.

This Virtex-5Q FPGA data sheet, part of an overall set of documentation on the Virtex-5 family of FPGAs, is available on the Xilinx website:???

DS174, Virtex-5Q Family OverviewUG190, Virtex-5 FPGA User GuideUG191, Virtex-5 FPGA Configuration Guide

?????????

UG192, Virtex-5 FPGA System Monitor User GuideUG193, Virtex-5 FPGA XtremeDSP? DesignConsiderations User Guide

UG194, Virtex-5 FPGA Embedded Tri-Mode EthernetMAC User Guide

UG195, Virtex-5 FPGA Packaging and PinoutSpecification

UG196, Virtex-5 FPGA RocketIO? GTP TransceiverUser Guide

UG197, Virtex-5 FPGA Integrated Endpoint Block UserGuide for PCI Express? Designs

UG198, Virtex-5 FPGA RocketIO GTX TransceiverUser Guide

UG200, Embedded Processor Block in Virtex-5 FPGAsReference Guide

UG203, Virtex-5 FPGA PCB Designer’s Guide

All specifications are subject to change without notice.

Virtex-5Q FPGA DC Characteristics

Table 1:Absolute Maximum Ratings(1)

SymbolVCCINTVCCAUXVCCOVBATTVREF

Description

Internal supply voltage relative to GNDAuxiliary supply voltage relative to GNDOutput drivers supply voltage relative to GNDKey memory battery backup supplyInput reference voltage

3.3V I/O input voltage relative to GND(2) (user and dedicated I/Os)

3.3V I/O input voltage relative to GND (restricted to maximum of 100 user I/Os)(4)2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)

Range–0.5 to 1.1–0.5 to 3.0–0.5 to 3.75–0.5 to 4.05–0.5 to 3.75–0.75 to 4.05–0.85 to 4.3

(Industrial Temperature)

UnitsVVVVVVVVmAmAVV°C

VIN(3)

–0.75 to VCCO+0.5

±100±100–0.75 to 4.05–0.75 to VCCO+0.5

–65to150

IINVTSTSTG

Current applied to an I/O pin, powered or unpoweredTotal current applied to all I/O pins, powered or unpoweredVoltage applied to 3-state 3.3V output(2) (user and dedicated I/Os)Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os)Storage temperature (ambient)

DS714 (v2.2) January 17, 2011Product Specification

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics

Table 57:IOB 3-state ON Output Switching Characteristics (TIOTPHZ)

Symbol

TIOTPHZ

Description

T input to Pad high-impedance

Speed Grade

-2I1.01

-1I1.12

-1M1.12

Unitsns

I/O Standard Adjustment Measurement Methodology

Input Delay Measurements

Table58 shows the test setup parameters used for measuring input delay.Table 58:Input Delay Measurement Methodology

DS714 (v2.2) January 17, 2011Product Specification

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics

Output Delay Measurements

Output delays are measured using a Tektronix P6245

TDS500/600 probe (<1pF) across approximately 4\microstrip trace. Standard termination was used for all testing. The propagation delay of the 4\

characterized separately and subtracted from the final measurement, and is therefore not included in the

generalized test setups shown in Figure11 and Figure12.

X-Ref Target - Figure 11X-Ref Target - Figure 12FPGA Output+CREFRREFVMEAS–ds714_12_012109VREFFigure 12:Differential Test Setup

Measurements and test conditions are reflected in the IBIS models except where the IBIS format precludes it.

Parameters VREF, RREF, CREF, and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using the following method:

1.Simulate the output driver of choice into the generalized

test setup, using values from Table59.2.Record the time to VMEAS.

3.Simulate the output driver of choice into the actual PCB

trace and load, using the appropriate IBIS model or capacitance value to represent the load.4.Record the time to VMEAS.

5.Compare the results of step2 and step4. The increase

or decrease in delay yields the actual propagation delayof the PCB trace.

FPGA OutputRREFVMEAS(voltage level when taking delay measurement)CREF (probe capacitance)DS714_11_012109Figure 11:Single Ended Test Setup

Table 59:Output Delay Measurement Methodology

Description

LVTTL (Low-Voltage Transistor-Transistor Logic)LVCMOS (Low-Voltage CMOS), 3.3VLVCMOS, 2.5VLVCMOS, 1.8VLVCMOS, 1.5VLVCMOS, 1.2V

PCI (Peripheral Component Interface), 33 MHz, 3.3VPCI, 66 MHz, 3.3VPCI-X, 133 MHz, 3.3V

GTL (Gunning Transceiver Logic)GTL Plus

HSTL (High-Speed Transceiver Logic), Class IHSTL, Class IIHSTL, Class III

DS714 (v2.2) January 17, 2011Product Specification

I/O StandardAttribute

LVTTL (all)LVCMOS33LVCMOS25LVCMOS18LVCMOS15LVCMOS12

PCI33_3 (rising edge)PCI33_3 (falling edge)PCI66_3 (rising edge)PCI66_3 (falling edge)PCIX (rising edge)PCIX (falling edgeGTLGTLPHSTL_IHSTL_IIHSTL_III

RREF (?)1M1M1M1M1M1M2525252525252525502550

CREF(1)(pF)00000010(2)10(2)10(2)10(2)10(3)10(3)00000

VMEAS(V)1.41.651.250.90.750.60.942.030.942.030.942.030.81.0VREFVREF0.9

VREF(V)00000003.303.33.31.21.50.750.751.5

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics

Input/Output Delay Switching Characteristics

Table 64:Input/Output Delay Switching Characteristics

Symbol

IDELAYCTRLTIDELAYCTRLCO_RDYFIDELAYCTRL_REFTIDELAYCTRL_RPWIODELAY

TIDELAYRESOLUTION

IODELAY Chain Delay Resolution

Pattern dependent period jitter in delay chain for clock pattern

Pattern dependent period jitter in delay chain for random data pattern (PRBS 23)

Maximum frequency of CLK input to IODELAYCE pin Setup/Hold with respect to CKINC pin Setup/Hold with respect to CKRST pin Setup/Hold with respect to CK

TSCONTROL delay to MUXE/MUXF switching and through IODELAY

Propagation delay through IODELAYPropagation delay through IODELAY

0±52500.34–0.060.200.040.28–0.12Note3Note3Note3

1/(64xFREFx1e6)(1)

0±52500.42–0.060.240.060.33–0.12Note3Note3Note3

psNote2Note2MHznsnsns

Reset to Ready for IDELAYCTRLREFCLK frequencyMinimum Reset pulse width

3.00200.00±1050.00

μsMHzMHzns

Description

Speed Grade-2I

-1I

-1M

Units

IDELAYCTRL_REF_PRECISIONREFCLK precision

TIDELAYPAT_JIT

TIODELAY_CLK_MAXTIODCCK_CE/ TIODCKC_CETIODCK_INC/ TIODCKC_INCTIODCK_RST/ TIODCKC_RSTTIODDO_TTIODDO_IDATAINTIODDO_ODATAIN

Notes:

1.Average Tap Delay at 200MHz=78ps.

2.Units in ps, peak-to-peak per tap, in High Performance mode.

3.Delay depends on IODELAY tap setting. See TRACE report for actual values.

CLB Switching Characteristics

Table 65:CLB Switching Characteristics

SymbolCombinatorial DelaysTILO

An–Dn LUT address to A

An–Dn LUT address to AMUX/CMUXAn–Dn LUT address to BMUX_A

TITOTAXATAXBTAXCTAXDTBXB

An–Dn inputs to A–D Q outputsAX inputs to AMUX outputAX inputs to BMUX outputAX inputs to CMUX outputAX inputs to DMUX outputBX inputs to BMUX output

0.090.220.350.770.440.520.360.620.41

0.100.250.400.900.530.610.420.730.48

ns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Maxns, Max

Description

Speed Grade

-2I

-1I

-1M

Units

DS714 (v2.2) January 17, 2011Product Specification

Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics

Table 68:Block RAM and FIFO Switching Characteristics (Cont’d)

Symbol

Maximum FrequencyFMAX

FMAX_CASCADEFMAX_FIFOFMAX_ECCNotes:

1.2.3.4.5.6.7.8.9.10.11.

TRACE will report all of these parameters as TRCKO_DO.

TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters.These parameters also apply to synchronous FIFO with DO_REG=0.

TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters.

These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG=1.

TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR.TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT.

The ADDR setup and hold must be met when EN is asserted even though WE is deasserted. Otherwise, block RAM data corruption is possible.TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B.These parameters also apply to RDEN.

TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.

Description

Speed Grade-2I500450500375

-1I450400450325

-1M450400450325

Units

Block RAM in all modes

Block RAM in cascade configurationFIFO in all modes

Block RAM and FIFO in ECC configuration

MHzMHzMHzMHz

DSP48E Switching Characteristics

Table 69:DSP48E Switching Characteristics

Symbol

Description

Speed Grade-2I0.210.230.160.31

-1I0.260.300.200.37

-1M0.260.300.200.50

Units

Setup and Hold Times of Data/Control Pins to the Input Register ClockTDSPDCK_{AA, BB, ACINA, BCINB}/TDSPCKD_{AA, BB, ACINA, BCINB}TDSPDCK_CC/TDSPCKD_CC

{A, B, ACIN, BCIN} input to {A, B} register CLK C input to Cregister CLK

nsns

Setup and Hold Times of Data Pins to the Pipeline Register ClockTDSPDCK_{AM, BM, ACINM, BCINM}/TDSPCKD_{AM, BM, ACINM, BCINM}

{A, B, ACIN, BCIN} input to Mregister CLK

1.440.19

1.710.19

Setup and Hold Times of Data/Control Pins to the Output Register ClockTDSPDCK_{AP, BP, ACINP, BCINP}_M/TDSPCKD_{AP, BP, ACINP, BCINP}_MTDSPDCK_{AP, BP, ACINP, BCINP}_NM/TDSPCKD_{AP, BP, ACINP, BCINP}_NMTDSPDCK_CP/TDSPCKD_CPTDSPDCK_{PCINP, CRYCINP, MULTSIGNINP}/

TDSPCKD_{PCINP, CRYCINP, MULTSIGNINP}

{A, B, ACIN, BCIN} input to Pregister CLK using multiplier

{A, B, ACIN, BCIN} input to Pregister CLK not using multiplier

C input to Pregister CLK

{PCIN, CARRYCASCIN, MULTSIGNIN} input to Pregister CLK

2.74–0.301.54–0.101.42–0.131.170.11

3.25–0.301.83–0.101.70–0.131.310.11

nsnsnsns

Setup and Hold Times of the CE Pins

{CEA1, CEA2A, CEB1B, CEB2B} input to TDSPCCK_{CEA1A, CEA2A, CEB1B,

{A,B} register CLKCEB2B}/

TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B}TDSPCCK_CECC/TDSPCKC_CECCTDSPCCK_CEMM/TDSPCKC_CEMM