MEMORY存储芯片ADM3202ARNZ-REEL中文规格书 - 图文

Device Command Codes

The system CPU provides control of all in-system READ, WRITE, and ERASE operationsof the device via the system bus. The device manages all block-erase and word-programalgorithms.

Device commands are written to the CUI to control all device operations. The CUI doesnot occupy an addressable memory location; it is the mechanism through which thedevice is controlled.

Note: For a dual device, all setup commands should be re-issued to the device when adifferent die is selected.

Table 10: Command Codes and Definitions

ModeReadDevice ModeRead arrayRead status registerCode0xFF0x70DescriptionPlaces the device in read array mode. Array data is output on DQ[15:0].Places the device in read status register mode. The device enters thismode after a PROGRAM or ERASE command is issued. Status registerdata is output on DQ[7:0].Places device in read device identifier mode. Subsequent reads outputmanufacturer/device codes, configuration register data, block lock sta-tus, or protection register data on DQ[15:0].Places the device in read CFI mode. Subsequent reads output CFI infor-mation on DQ[7:0].The device sets status register error bits. The clear status register com-mand is used to clear the SR error bits.First cycle of a 2-cycle programming command; prepares the CUI for aWRITE operation. On the next write cycle, the address and data arelatched and the device executes the programming algorithm at the ad-dressed location. During PROGRAM operations, the device respondsonly to READ STATUS REGISTER and PROGRAM SUSPEND commands.CE# or OE# must be toggled to update the status register in asynchro-nous read. CE# or ADV# must be toggled to update the status registerdata for synchronous non-array reads. The READ ARRAY commandmust be issued to read array data after programming has finished.This command loads a variable number of words up to the buffer sizeof 512 words onto the program buffer.The CONFIRM command is issued after the data streaming for writinginto the buffer is completed. The device then performs the bufferedprogram algorithm, writing the data from the buffer to the memoryarray.First cycle of a two-cycle command; initiates buffered enhanced factoryprogram mode (BEFP). The CUI then waits for the BEFP CONFIRM com-mand, 0xD0, that initiates the BEFP algorithm. All other commands areignored when BEFP mode begins.If the previous command was BEFP SETUP (0x80), the CUI latches theaddress and data, and prepares the device for BEFP mode.Read device ID orread configurationregisterRead CFIClear status registerWriteWord program setup0x900x980x500x40Buffered programBuffered programconfirm0xE80xD0BEFP setup0x80BEFP confirm0xD0PDF: 09005aef84566799

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Erase Operations

Erase Operations

BLOCK ERASE Command

ERASE operations are performed on a block basis. An entire block is erased each time aBLOCK ERASE command sequence is issued, and only one block is erased at a time.When a block is erased, each bit within that block reads as a logical 1.

A BLOCK ERASE operation is initiated by writing the BLOCK ERASE SETUP commandto the address of the block to be erased, followed by the BLOCK ERASE CONFIRM com-mand. If the device is placed in standby (CE# de-asserted) during a BLOCK ERASE oper-ation, the device completes the operation before entering standby. The VPP value mustbe above VPPLK and the block must be unlocked.

During a BLOCK ERASE operation, the device executes a sequence of internally-timedevents that conditions, erases, and verifies all bits within the block. Erasing the arraychanges the value in each cell from a 1 to a 0. Memory block array cells that with a valueof 1 can be changed to 0 only by programming the block.

The status register can be examined for block erase progress and errors by reading anyaddress. The device remains in the read status register state until another command iswritten. SR0 indicates whether the addressed block is erasing. SR7 is set upon erasecompletion.

SR7 indicates block erase status while the sequence executes. When the BLOCK ERASEoperation has completed, SR5 = 1 (set) indicates an erase failure. SR3 = 1 indicates thatthe device could not perform the BLOCK ERASE operation because VPP was outside ofits acceptable limits. SR1 = 1 indicates that the BLOCK ERASE operation attempted toerase a locked block, causing the operation to abort.

Before issuing a new command, the status register contents should be examined andthen cleared using the CLEAR STATUS REGISTER command. Any valid command canfollow after the BLOCK ERASE operation has completed.

The BLOCK ERASE operation is aborted by performing a reset or powering down thedevice. In either case, data integrity cannot be ensured, and it is recommended to eraseagain the blocks aborted.

BLANK CHECK Command

The BLANK CHECK operation determines whether a specified main block is blank; thatis, completely erased. Other than a BLANK CHECK operation, only a BLOCK ERASE op-eration can ensure a block is completely erased. BLANK CHECK is especially usefulwhen a BLOCK ERASE operation is interrupted by a power loss event.

A BLANK CHECK operation can apply to only one block at a time. The only operationallowed simultaneously is a READ STATUS REGISTER operation. SUSPEND and RE-SUME operations and a BLANK CHECK operation are mutually exclusive.

A BLANK CHECK operation is initiated by writing the BLANK CHECK SETUP commandto the block address, followed by the CHECK CONFIRM command. When a successfulcommand sequence is entered, the device automatically enters the read status state.The device then reads the entire specified block and determines whether any bit in theblock is programmed or over-erased.

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Erase Operations

BLANK CHECK operation progress and errors are determined by reading the status reg-ister at any address within the block being accessed. SR7 = 0 is a BLANK CHECK busystatus. SR7 = 1 is a BLANK CHECK operation complete status. The status register shouldbe checked for any errors and then cleared. If the BLANK CHECK operation fails, mean-ing the block is not completely erased, SR5 = 1. CE# or OE# toggle (during polling) up-dates the status register.

The READ STATUS REGISTER command must always be followed by a CLEAR STATUSREGISTER command. The device remains in status register mode until another com-mand is written to the device. Any command can follow once the BLANK CHECK com-mand is complete.

ERASE SUSPEND Command

The ERASE SUSPEND command suspends a BLOCK ERASE operation that is in pro-gress, enabling access to data in memory locations other than the one being erased. TheERASE SUSPEND command can be issued to any device address. A BLOCK ERASE oper-ation can be suspended to perform a WORD or BUFFER PROGRAM operation, or aREAD operation within any block except the block that is erase suspended.

When a BLOCK ERASE operation is executing, issuing the ERASE SUSPEND commandrequests the device to suspend the erase algorithm at predetermined points. The devicecontinues to output status register data after the ERASE SUSPEND command is issued.Block erase is suspended when SR[7,6] are set.

To read data from the device (other than an erase-suspended block), the READ ARRAYcommand must be issued. During erase suspend, a PROGRAM command can be issuedto any block other than the erase-suspended block. Block erase cannot resume untilprogram operations initiated during erase suspend complete. READ ARRAY, READ STA-TUS REGISTER, READ DEVICE IDENTIFIER, READ CFI, and ERASE RESUME are validcommands during erase suspend. Additionally, CLEAR STATUS REGISTER, PROGRAM,PROGRAM SUSPEND, BLOCK LOCK, BLOCK UNLOCK, and BLOCK LOCK DOWN arevalid commands during an ERASE SUSPEND operation.

During an erase suspend, de-asserting CE# places the device in standby, reducing activecurrent. VPP must remain at a valid level, and WP# must remain unchanged while inerase suspend. If RST# is asserted, the device is reset.

ERASE RESUME Command

The ERASE RESUME command instructs the device to continue erasing, and automati-cally clears SR[7,6]. This command can be written to any address. If status register errorbits are set, the status register should be cleared before issuing the next instruction.RST# must remain de-asserted.

Erase Protection

When VPP = VIL, absolute hardware erase protection is provided for all device blocks. IfVPP is at or below VPPLK, ERASE operations halt and SR3 is set indicating a VPP-level er-ror.

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Security Operations

Figure 12: Block Locking State Diagram

[000]D0h01h[001]2Fh(Power-up/Reset default)Program/Erase Prevented

WP# = VIL = 0

(Locked down)Program/Erase Allowed

WP# = VIL = 0

WP# toggle[010]2FhD0h, 01h, or 2Fh[011]WP# toggle(Virtual lock-down)[110]Program/Erase Allowed

WP# = VIH = 1

[100]D0h01h/2Fh2Fh[111](Lock downdisabled,WP# = VIH)2FhD0h01h[101](Power-up/Reset default)Program/Erase Prevented

WP# = VIH = 1

Note:

1.D0h = UNLOCK command; 01h = LOCK command; 60h (not shown) LOCK SETUP com-mand; 2Fh = LOCK DOWN command.

Block Locking During Suspend

Block lock and unlock changes can be performed during an erase suspend. To change

block locking during an ERASE operation, first issue the ERASE SUSPEND command.Monitor the status register until SR7 and SR6 are set, indicating the device is suspendedand ready to accept another command.

Next, write the desired lock command sequence to a block, which changes the lockstate of that block. After completing BLOCK LOCK or BLOCK UNLOCK operations, re-sume the ERASE operation using the ERASE RESUME command.Note:

A BLOCK LOCK SETUP command followed by any command other than BLOCK LOCK,BLOCK UNLOCK, or BLOCK LOCK DOWN produces a command sequence error andset SR4 and SR5. If a command sequence error occurs during an erase suspend, SR4 andSR5 remains set, even after the erase operation is resumed. Unless the Status Register iscleared using the CLEAR STATUS REGISTER command before resuming the ERASE op-eration, possible erase errors may be masked by the command sequence error.If a block is locked or locked-down during an erase suspend of the same block, the lockstatus bits change immediately. However, the ERASE operation completes when it is re-sumed. BLOCK LOCK operations cannot occur during a program suspend.

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Security Operations

Selectable OTP Blocks

The OTP security feature on the device is backward-compatible to the earlier genera-tion devices. Contact your local Micron representative for details about its implementa-tion.

Password Access

The password access is a security enhancement offered on the device. This feature pro-tects information stored in array blocks by preventing content alteration or reads until avalid 64-bit password is received. The password access may be combined with nonvola-tile protection and/or volatile protection to create a multi-tiered solution.Contact your Micron sales office for further details concerning password access.

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