FPGA可编程逻辑器件芯片EP1S10F484C5N中文规格书 - 图文

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For detailed information on differential I/O standards, refer to the

High-Speed Differential I/O Interfaces with DPA in StratixII & StratixIIGX Devices chapter in volume 2 of the StratixII Device Handbook or

High-Speed Differential I/O Interfaces with DPA in StratixII & StratixIIGX Devices chapter in volume 2 of the StratixIIGX Device Handbook.

Differential SSTL-2 Class I and Differential SSTL-2 Class II

The 2.5-V differential SSTL-2 standard is formulated under JEDEC Standard, JESD8-9A: Stub Series Terminated Logic for 2.5-V (SSTL_2).This I/O standard is a 2.5-V standard used for applications such as high-speed DDR SDRAM clock interfaces. This standard supports differential signals in systems using the SSTL-2 standard and

supplements the SSTL-2 standard for differential clocks. StratixII and StratixIIGX devices support both input and output levels. Figures4–10 and 4–11 shows details on differential SSTL-2 termination.1

StratixII and StratixIIGX devices support differential SSTL-2 I/O standards in pseudo-differential mode, which is implemented by using two SSTL-2 single-ended buffers.

The Quartus?II software only supports pseudo-differential standards on the INCLK, FBIN and EXTCLK ports of enhanced PLL, as well as on DQS pins when DQS megafunction (ALTDQS, Bidirectional Data Strobe) is used. Two single-ended output buffers are automatically programmed to have opposite polarity so as to implement a pseudo-differential output. A proper VREF voltage is required for the two single-ended input buffers to implement a pseudo-differential input. In this case, only the positive polarity input is used in the speed path while the negative input is not connected internally. In other words, only the non-inverted pin is required to be specified in your design, while the QuartusII software automatically generates the inverted pin for you.

Although the QuartusII software does not support pseudo-differential SSTL-2 I/O standards on the left and right I/O banks, you can implement these standards at these banks. You need to create two pins in the designs and configure the pins with single-ended SSTL-2 standards. However, this is limited only to pins that support the differential pin-pair I/O function and is dependent on the single-ended SSTL-2 standards support at these banks.

Stratix II Device Handbook, Volume 2

StratixII and StratixIIGX I/O Standards Support

Figure4–10.Differential SSTL-2 Class I Termination

VTT = 1.25 VVTT = 1.25 VDifferentialTransmitter25 Ω50 Ω50 ΩDifferentialReceiver Z0 = 50 Ω25 ΩZ0 = 50 ΩFigure4–11.Differential SSTL-2 Class II Termination

VTT = 1.25 VVTT = 1.25 VVTT = 1.25 VVTT = 1.25 VDifferentialTransmitter50 Ω25 Ω50 Ω50 Ω50 ΩDifferentialReceiver Z0 = 50 Ω25 ΩZ0 = 50 ΩDifferential SSTL-18 Class I and Differential SSTL-18 Class II

The 1.8-V differential SSTL-18 standard is formulated under JEDEC Standard, JESD8-15: Stub Series Terminated Logic for 1.8-V (SSTL_18).The differential SSTL-18 I/O standard is a 1.8-V standard used for

applications such as high-speed DDR2 SDRAM interfaces. This standard supports differential signals in systems using the SSTL-18 standard and supplements the SSTL-18 standard for differential clocks.1

StratixII and StratixIIGX devices support both input and output levels operation.

Stratix II Device Handbook, Volume 2

StratixII and StratixIIGX I/O Standards Support

Stratix II Device Handbook, Volume 2

Selectable I/O Standards in StratixII and StratixIIGX Devices

Figure4–17.1.5-V Differential HSTL Class II Termination

VTT = 0.75 VVTT = 0.75 VVTT = 0.75 VVTT = 0.75 VDifferentialTransmitter50 Ω50 Ω50 Ω50 ΩDifferentialReceiver Z0 = 50 ΩZ0 = 50 ΩLVDS

The LVDS standard is formulated under ANSI/TIA/EIA Standard, ANSI/TIA/EIA-644: Electrical Characteristics of Low Voltage Differential Signaling Interface Circuits.

The LVDS I/O standard is a differential high-speed, low-voltage swing, low-power, general-purpose I/O interface standard. In StratixII devices, the LVDS I/O standard requires a 2.5-V VCCIO level for the side I/O pins in banks 1, 2, 5, and 6. The top and bottom banks have different VCCIO requirements for the LVDS I/O standard. The LVDS clock I/O pins in banks 9 through 12 require a 3.3-V VCCIO level. Within these banks, the PLL[5,6,11,12]_OUT[1,2] pins support output only LVDS

operations. The PLL[5,6,11,12]_FB/OUT2 pins support LVDS input or output operations but cannot be configured for bidirectional LVDS operations. The LVDS clock input pins in banks 4, 5, 7, and 8 use VCCINT and have no dependency on the VCCIO voltage level. This standard is used in applications requiring high-bandwidth data transfer, backplane drivers, and clock distribution. The ANSI/TIA/EIA-644 standard specifies LVDS transmitters and receivers capable of operating at

recommended maximum data signaling rates of 655megabit per second (Mbps). However, devices can operate at slower speeds if needed, and there is a theoretical maximum of 1.923 Gbps. StratixII and StratixII GX devices are capable of running at a maximum data rate of 1 Gbps and still meet the ANSI/TIA/EIA-644 standard.

Because of the low-voltage swing of the LVDS I/O standard, the electromagnetic interference (EMI) effects are much smaller than complementary metal-oxide semiconductor (CMOS),

transistor-to-transistor logic (TTL), and positive (or psuedo) emitter coupled logic (PECL). This low EMI makes LVDS ideal for applications

Stratix II Device Handbook, Volume 2

Selectable I/O Standards in StratixII and StratixIIGX Devices

StratixIIGX devices have 6 general I/O banks and 4 enhanced

phase-locked loop (PLL) external clock output banks (Figure4–22). I/O banks 9 through 12 are enhanced PLL external clock output banks located on the top and bottom of the device.

Figure4–22.StratixIIGX I/O Banks Notes(1), (2), (3), (4)

DQSx8PLL7VREF0B2VREF1B2VREF2B2VREF3B2VREF4B2DQSx8DQSx8Bank 3DQSx8VREF0B3VREF1B3VREF2B3VREF3B3VREF4B3PLL11Bank 11PLL5Bank 9DQSx8DQSx8DQSx8DQSx8Bank 4DQSx8VREF0B4VREF1B4VREF2B4VREF3B4VREF4B4This I/O bank supports LVDS and LVPECLThis I/O bank supports LVDS and LVPECLstandards for input clock operation. standards for input clock operations. Differential HSTL and differential SSTL Differential HSTL and differential SSTL standards are supported for both input standards are supported for both input and output operations. (3) and output operations. (3) I/O Banks 3, 4, 9 & 11 support all single-ended I/O standards for both input and output operation. All differential I/O standards are supported for both input and output operation at I/O banks 9 & 10.I/O Banks 1, & 2, support LVTTL, LVCMOS, 2.5 -V, 1.9 -]V, 1.5 -V, SSTL -2, SSTL-18 class I, LVDS, pseudo-differential SSTL -2, and pseudo-differential SSTL-18 class I standards for both input and output operations. HSTL, SSTL-18 class II, pseudo-differential HSTL, and pseudo-differential SSTL-18 class II standards are only supported for input operations. (4)I/O Banks 7, 8, 10 and 12 support all single-ended I/O standards for both input and output operation. All differential I/O standards are supported for both input and output operations at I/O bank 10 and 12. Bank 2PLL1PLL2VREF0B1VREF1B1VREF2B1VREF3B1VREF4B1Bank 1This I/O bank supports LVDS and LVPECLstandards for input clock operations. Differential HSTL and differential SSTL standards are supported for both input and output operations. (3) Bank 8This I/O bank supports LVDS and LVPECLstandards for input clock operations. Differential HSTL and differential SSTL standards are supported for both input and output operations. (3) Bank 12PLL12Bank 10PLL6DQSx8DQSx8Bank 7VREF4B7VREF3B7VREF2B7VREF1B7VREF0B7PLL8VREF4B8VREF3B8VREF2B8VREF1B8VREF0B8DQSx8DQSx8DQSx8DQSx8DQSx8DQSx8DQSx8Notes to Figure4–22:(1)(2)(3)(4)

Figure4–22 is a top view of the silicon die which corresponds to a reverse view for flip-chip packages. It is agraphical representation only.

Depending on size of the device, different device members have different number of VREF groups. Refer to the pin list and the QuartusII software for exact locations.

Banks 9 through 12 are enhanced PLL external clock output banks.

Horizontal I/O banks feature transceiver and DPA circuitry for high speed differential I/O standards. Refer to the High-Speed Differential I/O Interfaces with DPA in StratixII & Stratix IIGX Devices chapter in volume 2 of theStratixIIGX Device Handbook, or the StratixIIGX Transceiver User Guide (volume 1) of the Stratix II GX Device Handbook for more information on differential I/O standards.

QuartusII software does not support differential SSTL and differential HSTL standards at left/right I/O banks. Refer to the “Differential I/O Standards” on page4–10 if you need to implement these standards at these I/O banks.Banks 11 and 12 are available only in EP2SGX60C/D/E, EP2SGX90E/F, and EP2SGX130G.PLLs 7,8,11, and 12 are available only in EP2SGX60C/D/E, EP2SGXE/F, and EP2SGX130G.

(5)(6)(7)

Stratix II Device Handbook, Volume 2

Bank 15Bank 16Bank 17Bank 14Bank 13