DC & Switching Characteristics
High-Speed I/O Specifications
Table5–88 provides high-speed timing specifications definitions.
Table5–88.High-Speed Timing Specifications & DefinitionsHigh-Speed Timing Specifications
tCfHSCLKJWtRISEtFALL
Timing unit interval (TUI)
Definitions
High-speed receiver/transmitter input and output clock period.High-speed receiver/transmitter input and output clock frequency.Deserialization factor (width of parallel data bus).PLL multiplication factor.Low-to-high transmission time.High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency × Multiplication Factor) = tC/w).
Maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA.Maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA.The timing difference between the fastest and slowest output edges, including tCO variation and clock skew. The clock is included in the TCCS measurement.
The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window.
Peak-to-peak input jitter on high-speed PLLs.Peak-to-peak output jitter on high-speed PLLs.Duty cycle on high-speed transmitter output clock.Lock time for high-speed transmitter and receiver PLLs.
fHSDRfHSDRDPA
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitterOutput jittertDUTYtLOCK
Table5–89 shows the high-speed I/O timing specifications for -3 speed grade StratixII devices.
Table5–89.High-Speed I/O Specifications for -3 Speed Grade (Part 1 of2)
Symbol
Conditions
Notes(1), (2)-3 Speed GradeMin
1616150
TypMax
520500717
Unit
MHzMHzMHz
fHSCLK (clock frequency) W = 2 to 32 (LVDS, HyperTransport technology)
(3)fHSCLK = fHSDR / W
W = 1 (SERDES bypass, LVDS only)W = 1 (SERDES used, LVDS only)
Stratix II Device Handbook, Volume 1
ContentsStratix II Device Handbook, Volume1
vi
DC & Switching Characteristics
Table5–90 shows the high-speed I/O timing specifications for -4 speed grade StratixII devices.
Table5–90.High-Speed I/O Specifications for -4 Speed Grade
Symbol
Conditions
Notes(1), (2)
-4 Speed GradeMin
1616150150(4)(4)150-330
TypMax
5205007171,0407605001,040200-190160180
Unit
MHzMHzMHzMbpsMbpsMbpsMbpspspspspsps%UIUINumber of repetitions
fHSCLK (clock frequency) W = 2 to 32 (LVDS, HyperTransport technology)
(3)fHSCLK = fHSDR / W
W = 1 (SERDES bypass, LVDS only)W = 1 (SERDES used, LVDS only)
fHSDR (data rate)
J = 4 to 10 (LVDS, HyperTransport technology)J = 2 (LVDS, HyperTransport technology)J = 1 (LVDS only)
fHSDRDPA (DPA data rate)J = 4 to 10 (LVDS, HyperTransport technology)TCCSSWOutput jitterOutput tRISEOutput tFALLtDUTY
DPA run lengthDPA jitter toleranceDPA lock time
Data channel peak-to-peak jitter
StandardSPI-4Parallel Rapid I/OMiscellaneous
Training
Pattern0000000000111111111100001111100100001010101001010101
Notes to Table5–90:(1)(2)(3)(4)
All differential standardsAll differential standardsAll differential I/O standardsAll differential I/O standards
45 5055 6,400
0.44
Transition Density10%P0%
256256256256256
When J = 4 to 10, the SERDES block is used.When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ? input clock frequency × W ? 1,040.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not have a minimum toggle rate.
Stratix II Device Handbook, Volume 1
StratixII Device Family Data SheetStratix II Device Handbook, Volume 1
Section I–2
DC & Switching Characteristics
Table5–102 shows the JTAG timing parameters and values for StratixII devices.
Table5–102.StratixII JTAG Timing Parameters & ValuesSymbol
tJCPtJCHtJCLtJPSUtJPHtJPCOtJPZXtJPXZ(1)
Parameter
TCK clock periodTCK clock high timeTCK clock low time
JTAG port setup timeJTAG port hold timeJTAG port clock to output
JTAG port high impedance to valid outputJTAG port valid output to high impedance
Min
30131335
MaxUnit
nsnsnsnsns
11 (1)14 (1)14 (1)
nsnsns
Note to Table5–102:
A 1ns adder is required for each VCCIO voltage step down from 3.3V. Forexample, tJPCO = 12ns if VCCIO of the TDO I/O bank = 2.5V, or 13ns if it equals 1.8V.
Document
Revision History
Table5–103 shows the revision history for this chapter.
Table5–103.Document Revision History (Part 1 of3)Date and Document Version
July 2009, v4.4
Changes Made
Updated Table5–92.
Summary of Changes
Updated the spread spectrum modulation frequency (fSS) from (100kHz–500kHz) to (30kHz–150kHz).
—
May 2007, v4.3
●●●
Updated RCONF in Table5–4.Updated fIN (min) in Table5–92.
Updated fIN and fINPFD in Table5–93.
Moved the Document Revision History section to the end of the chapter.
August, 2006, v4.2
Updated Table5–73, Table5–75, Table5–77,
Table5–78, Table5–79, Table5–81, Table5–85, and Table5–87.
——
Stratix II Device Handbook, Volume 1
FPGA可编程逻辑器件芯片EP2SGX60DF780C3中文规格书 - 图文
