Packaging Overview
About this Guide
Xilinx? 7 series FPGAs include four FPGA families that are all designed for lowest power to enable a common design to scale across families for optimal power, performance, and cost. The Spartan?-7 family is the lowest density with the lowest cost entry point into the
7 series portfolio. The Artix?-7 family is optimized for highest performance-per-watt and bandwidth-per-watt for cost-sensitive, high-volume applications. The Kintex?-7 family is an innovative class of FPGAs optimized for the best price-performance. The Virtex?-7 family is optimized for highest system performance and capacity.
This 7 series packaging and pinout product specification, part of an overall set of documentation on the 7 series FPGAs, is available on the Xilinx website.
Introduction
This section describes the pinouts for the 7 series FPGAs in various fine pitch and flip-chip 1.0 mm pitch BGA packages, 0.8 mm and 0.5 mm pitch chip-scale packages, and 0.5 mm pitch wire-bond lead frame packages.
Spartan-7, Artix-7, and Kintex-7 devices are offered in low-cost, space-saving packages that are optimally designed for the maximum number of user I/Os.
Virtex-7 T and Virtex-7 XT devices are offered exclusively in high performance flip-chip BGA packages that are optimally designed for improved signal integrity and jitter.For pinout and packaging information on the Virtex-7 HT devices,
Package inductance is minimized as a result of optimal placement and even distribution as well as an increased number of Power and GND pins.
The FFG, FLG, FHG, FBG, SBG, and RFG flip-chip packages marked with the Pb-free Character on the upper right of the device are RoHS 6 of 6 compliant. The FFG, FLG, FHG, FBG, SBG, and RFG flip-chip packages not marked with the Pb-free character are RoHS 6 of 6 compliant,
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2024
Chapter 1:Packaging Overview
X-Ref Target - Figure 1-7Left I/OColumn BanksBank 16HRBank 15HRBank 14HRPLL02Right I/OColumnBanksCMTMMCM02PLL01PLL11HROWGTP Quad 216Bank 35HRQuadGTPCMTMMCM01PLL00CMT16 BUFGs16 BUFGsMMCM11PLL10Horizontal CenterCMTMMCM00CMTMMCM10Bank 34HRBank50 I/OsCMTBackboneClockingBackboneCMTBackboneUG475_c1_02_011714Figure 1-7:
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2024
XC7A50T, XA7A50T, and XQ7A50T Banks
Chapter 1:Packaging Overview
XC7A75T and XA7A75T Banks
Figure1-8 shows the I/O and transceiver banks.
FTG256 Package (XC7A75T only)
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HR I/O banks 13 and 16 are not bonded out.HR I/O bank 34 is partially bonded out.
The GTP Quads 213 and 216 are not bonded out.
CSG324 Package
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HR I/O bank 13 is not bonded out.HR I/O bank 16 is partially bonded out.
The GTP Quads 213 and 216 are not bonded out.
FGG484 Package
??
HR I/O bank 13 is partially bonded out.The GTP Quad 213 is not bonded out.
FGG676 Package (XC7A75T only)
All HR I/O banks and the GTP Quads are fully bonded out in this package.
X-Ref Target - Figure 1-8Left I/OColumn BanksBank 16HRBank 15HRBank 14HRBank 13HRPLL03Right I/OColumnBanksCMTMMCM03PLL02PLL11GTP Quad 216Bank 35HRQuadGTPCMTMMCM02 PLL01CMT16 BUFGs16 BUFGsMMCM11PLL10Horizontal CenterCMTMMCM01PLL00CMTMMCM10Bank 34HRBank50 I/OsCMTMMCM00HROWGTP Quad 213CMTBackboneClockingBackboneCMTBackboneUG475_c1_50_011714Figure 1-8:XC7A75T and XA7A75T Banks
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2024
Chapter 1:Packaging Overview
XC7K420T Banks
Figure1-16 shows the I/O and transceiver banks for the XC7K420T.
FFG901 and FFV901 Package
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HR I/O bank 18 is not fully bonded out.GTX Quad 118 is not bonded out.
FFG1156 and FFV1156 Package
All HR I/O banks and the GTX Quads are fully bonded out in this package.
X-Ref Target - Figure 1-16Left I/OColumn BanksBank 18HRBank 17HRBank 16HRBank 15HRBank 14HRBank 13HRBank 12HRBank 11HRPLL07CMTMMCM07PLL06GTX Quad 118QuadGTXCMTMMCM06PLL05GTX Quad 117CMTMMCM05PLL04GTX Quad 116CMTMMCM04PLL0316 BUFGs16 BUFGsGTX Quad 115HorizontalCenterCMTMMCM03PLL02GTX Quad 114CMTMMCM02PLL01GTX Quad 113CMTMMCM01PLL00GTX Quad 112HROWCMTMMCM00GTX Quad 111CMTBackboneClockingBackboneUG475_c1_13_042012Figure 1-16:XC7K420T Banks
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2024
Chapter 1:Packaging Overview
XC7V585T and XQ7V585T Banks
Figure1-18 shows the I/O and transceiver banks for the XC7V585T and XQ7V585T.
FFG1157 and RF1157 Packages
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All HR I/O banks (11, 12, and 13) are not bonded out.HP I/O banks 31, 32, and 33 are not bonded out.GTX Quads 111, 112, 113, and 119 are not bonded out.
FFG1761 and RF1761 Packages
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X-Ref Target - Figure 1-18HR I/O bank 11 is not bonded out.
All HP I/O banks and the GTX Quads are fully bonded out in these packages.
Left I/OColumn BanksBank 19HPBank 18HPBank 17HPBank 16HPBank 15HPBank 14HPBank 13HRPLL08PLL18Right I/OColumnBanksCMTMMCM08PLL07CMTMMCM18PLL17Bank 39HPBank 38HPBank 37HPBank 36HPBank 35HPBank 34HPBank 33HPBank 32HPBank 31HPGTX Quad 119CMTMMCM07PLL06CMTMMCM17PLL16GTX Quad 118CMTMMCM06PLL05CMTMMCM16PLL15GTX Quad 117CMTMMCM05PLL0416 BUFGs16 BUFGsCMTMMCM15PLL14GTX Quad 116CMTMMCM04PLL03CMTMMCM14PLL13GTX Quad 115CMTMMCM03PLL02CMTMMCM13PLL12GTX Quad 114CMTMMCM02PLL01CMTMMCM12PLL11GTX Quad 113Bank50 I/OsBank 12HRBank 11HRCMTMMCM01PLL00CMTMMCM11GTX Quad 112CMTMMCM00HROWPLL10CMTMMCM10GTX Quad 111Horizontal CenterClockingBackboneCMTBackboneUG475_c1_15_060711Figure 1-18:XC7V585T and XQ7V585T Banks
7 Series FPGAs PackagingUG475 (v1.18) July 16, 2024
FPGA可编程逻辑器件芯片XC6VLX75T-1FFG784C中文规格书 - 图文
